Diagrams; Block Diagram - Md Servo Section - Sony HCD-PX5 Service Manual

Q Q
3 7 6 3 1 5 1 5 0
6-1. BLOCK DIAGRAM – MD SERVO Section –
HR901
OVER WRITE HEAD
I I
1
J J
2
F
B
C B
I J
D A
A
A
4
B
5
E C
6
DETECTOR D
7
C
D
E E
8
F F
9
T E
LASER DIODE L 1 3 9 4 2 2 9 6 5 1 3
AUTOMATIC
APC
ILCC
POWER
11
CONTROL
Q121, 122
PD LD
LASER ON
PD PD
SWITCH 10
Q101
OPTICAL PICK-UP BLOCK
(KMS-262A/J1N)
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC141
6 OUT4F IN4R
M101
M
(SPINDLE)
8 OUT4R IN4F
27 OUT2F IN2F
M102
M
(SLED)
25 OUT2R IN2R
2-AXIS
DEVICE
FCS+
21 OUT1F IN1F
w w w
23 OUT1R IN1R
FCS–
.
TRK+
12 OUT3F IN3F
TRK–
10 OUT3R IN3R
MOD
HF MODULE
05
SECTION 6

DIAGRAMS

DIGITAL SIGNAL PROCESSOR,
EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER
OVER WRITE IC151 (1/2)
HEAD DRIVE
IC181, Q181, 182
SCTX
RF AMP,
FOCUS/TRACKING ERROR AMP
IC101
48 47
RFO AGCI RF
RF AGC
RF AMP 46 40 38
& EQ
EQ
AUX
B.P.F.
33
WBL
3T
TEMP
PEAK
37
PEAK &
BOTM
BOTTOM
36
WBL
ADFM ADIN
ADFG
AT
B.P.F. 29 30 32
AMP
I-V
ABCD
ABCD
AMP 35
AMP
FE
FOCUS
34
ERROR AMP
TE
26
I-V TRACKING
SE
AMP ERROR AMP
28
COMMAND
LD/PD
AMP
SERIAL/
PARALLEL
V-I
CONVERTER,
CONVERTER
DECODER
12 20 16 17 18
PSB 16
SPFD
3
SPRD
65 75
4 13 67 66
RECP
APCREF AUTOMATIC
83
POWER
CONTROL
SFDR ANALOG MUX
29 92
SRDR
30 91
A/D CONVERTER
DIGITAL
SERVO
SIGNAL
FROM CPU
PROCESS
FFDR
INTERFACE
19 88
FRDR
18 89
x a o
y
AUTO
SEQUENCER
i TFDR
14 86
DIGITAL SERVO
TRDR
15 85
SIGNAL PROCESSOR
IC151 (2/2)
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8
15
TX
EFMO
100
FILI
60
PCO
59
PLL
CLTV
62
FILO
61
ASYO
53
ASYI
54
COMPA-
RFI
RATOR
57
SUBCODE
PROCESSOR
ADIP
78 DEMODULATOR/
DECODER
F0CNT SPINDLE
INTERFACE
79
SERVO
Q Q
94 93 10 12 11 14 9 8
3 7 6 3
25 27 32 48 40
COMPARATOR
IC102
OP-LEVEL
133
29 LDON
47 DIG-RST
35
WRPWR
14 MOD
12 13
74 64
63
5 6
IN1 IN2
LOADING
MOTOR DRIVE
IC1004
OUT1 OUT2
2 10
M
M103
(LOADING)
XLRF XLAT
u 1 6 3 80
CKRF SCLK
81
DTRF SWDT
82
.
HF MODULE
SWITCH
Q131 – 134
49 49
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2 4
9 9 8
ADDT
25
DATAI
SAMPLING 22
RATE
XBCKI
CONVERTER BCK
24
LRCKI LRCK
23
DIN0
DIGITAL 19
DIN1
AUDIO
20
DOUT
INTERFACE
21
DADT
26
28 27 29
OSCI
16
CLOCK
OSCO
GENERATOR
17
INTERNAL BUS
CPU MONITOR
CONTROL
5 6 7 1 2 3 4
1 5 1 5 0 8 9 2 4
XOE
43
XWE
47
XRAS
46
XCAS
44
38 42 50 58 56
MD MECHANISM CONTROLLER LIMIT-IN
IC1001 (1/2)
REC-SW
OUT-SW
M+7V
REFERENCE
VREF 4 VOLTAGE SWITCH
Q1001, 1002
PLAY-SW 49
11 LD-LOW
REFLECT
m
EEPROM
PROTECT
IC195
c o
SDA 5 61 SDA
SCL 6 66 SCL
WP 7 60 EEP-WP
HCD-PX5
2
9 9
DADTI
A
(Page 50)
LRCK, BCK
B (Page 50)
DIN0
C
(Page 50)
DOUT
D
(Page 50)
X171
90.3168MHz
D-RAM
IC152
9 8 2 9 9
22 OE
4
WE
5 RAS • SIGNAL PATH
23 CAS
: MD PLAY
: MD REC
: CD PLAY
S101
(LIMIT IN)
S101
ON: When the optical pick-up is
30
inner position
S105
(REC POSITION)
S105
ON: When the over write head is
43
recording position
S103
(PACK OUT)
S103
ON: When the eject slider is
51
open position
S104
(PLAY POSITION)
S104
ON: When the eject slider is
playback position
S102-1
–1 (REFLECT RATE DETECT)
67
ON: When the high reflection
rate disc detect
68
–2
S102
S102-2
(PROTECT DETECT)
ON: When the REC-proof claw is
close (un-protect)