Http://Www.xiaoyu163.Com - Sony AVD-S10 Service Manual

AVD-S10
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• IC801 CXD2752R (Playback Signal Processor) (DVD Board)
Pin No. Pin Name
1 VSCA0
2 XMSLAT
3 MSCK
4 MSDATI
5 VDCA0
6 MSDATO
7 MSREADY
8 XMSDOE
9 XRST
10 SMUTE
11 MCKI
12 VSIOA0
13 EXCKO1
14 EXCKO2
15 LRCK
16 F75HZ
17 VDIOA0
18 to 25 MNT0 - 7
26 TCK
27 TDI
28 VSCA1
29 TDO
TE
L 13942296513
30 TMS
31 TRST
32 to 34 TEST1 - 3
35 VDCA1
36 UBIT
37 XBIT
38 to 41 SUPDT0 - 3
42 VSIOA1
43, 44 SUPDT4 - 5
45 VDIOA1
46, 47 SUPDT6 - 7
48 SUPEN
49 VSCA2
50 NC
51, 52 TEST4 - 5
53 NC
54 VDCA2
55, 56 NC
57 BCKASL
58 VXDSD0
59 BCKAI
60 BCKAO
61 PHREFI
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62 PHREFO
63 ZDFL
64 DSAL
.
65 ZDFR
66 DSAR
66

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I/O
– Ground
I Latch signal input for micom serial communication
I Shift clock input for micom serial communication
I Data input for micom serial communication
– Power supply
O Data output for micom serial communication
O Output ready flag output for micom serial communication
O Output enable signal output for micom serial communication
I Reset signal input
I Soft mute signal input (H:soft mute, L:off)
I Master clock input (768Fs 33.8688MHz)
– Ground for I/O
O External clock output 1
O External clock output 2 (not used)
O Clock output (1Fs 44.1kHz)(not used)
O Frame signal output
– Power supply for I/O
O Monitor signal output (not used)
I Test clock input (connected to ground)
I Input terminal for test
– Ground
O Output terminal for test (open)
I Input terminal for test (open)
I Reset terminal for test (open)
I Input terminal for test (connected to ground)
– Power supply
O Output terminal for test (open)
O DST monitor terminal (open)
O Supplementary data output (open)
– Ground for I/O
O Supplementary data output (open)
– Power supply for I/O
O Supplementary data output (open)
O Supplementary data acknoledge output (open)
– Ground
O Output terminal for test (open)
I Input terminal for test (connected to ground)
O Output terminal for test (open)
– Power supply
O Output terminal for test (open)
I Bit clock I/O selection signal input for DSD data output (L:slave, H:master)
– Ground for DSD data output
I Bit clock input for DSD data output (open)
O Bit clock output for DSD data output
I Phase reference signal input for DSD signal phase modulation (open)
O Phase reference signal output for DSD signal phase modulation (open)
x ao
O Lch zero data detection flag signal output (open) y
O Lch DSD data output
i
O Rch zero data detection flag signal output (open)
O Rch DSD data output
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