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The timing configuration is based on an internal reference clock, MCLK. The MCLK is generated out of
LCD_CLK, which is determined by the CLKDIV bit in the LCD_CTRL register:
See your device-specific data manual for the timing configurations supported by the LCD controller.
23.2.5 Raster Controller
Raster mode (and the use of this logic) is enabled by setting the MODESEL bit in the LCD control register
(LCD_CTRL).
Table 23-4
Interface
Passive (STN) Mono
4-bit
Passive (STN) Mono
8-bit
Passive (STN) Color
Active (TFT) Color
SPRUH91D – March 2013 – Revised September 2016
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MCLK + LCD_CLK when CLKDIV + 0.
LCD_CLK
MCLK +
CLKDIV
shows the active external signals when this mode is active.
Table 23-4. Operation Modes Supported by Raster Controller
Data Bus
Register Bits
Width
RASTER_CTRL[9, 7, 1]
4
001
8
101
8
100
16
x10
Copyright © 2013–2016, Texas Instruments Incorporated
when CLKDIV 0 0.
Signal Name
LCD_D[3:0]
LCD_PCLK
LCD_HSYNC
LCD_VSYNC
LCD_AC_ENB_CS
LCD_MCLK
LCD_D[7:0]
LCD_PCLK
LCD_HSYNC
LCD_VSYNC
LCD_AC_ENB_CS
LCD_MCLK
LCD_D[7:0]
LCD_PCLK
LCD_HSYNC
LCD_VSYNC
LCD_AC_ENB_CS
LCD_MCLK
LCD_D[15:0]
LCD_PCLK
LCD_HSYNC
LCD_VSYNC
LCD_AC_ENB_CS
LCD_MCLK
Liquid Crystal Display Controller (LCDC)
Architecture
Description
Data bus
Pixel clock
Horizontal clock(Line Clock)
Vertical clock (Frame Clock)
AC Bias
Not used
Data bus
Pixel clock
Horizontal clock(Line Clock)
Vertical clock (Frame Clock)
AC Bias
Not used
Data bus
Pixel clock
Horizontal clock(Line Clock)
Vertical clock (Frame Clock)
AC Bias
Not used
Data bus
Pixel clock
Horizontal clock(Line Clock)
Vertical clock (Frame Clock)
Output enable
Not used
939
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