Atmel XMEGA B User Manual

Atmel XMEGA B User Manual

8-bit microcontroller
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This document contains complete and detailed description of all modules included in the
®
®
®
Atmel
AVR
XMEGA
B microcontroller family. The Atmel AVR XMEGA B is a family of low-
power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the
AVR enhanced RISC architecture with integrated LCD controller. The available Atmel AVR
XMEGA B modules described in this manual are:
Atmel AVR CPU
Memories
DMAC - Direct memory access controller
Event system
System clock and clock options
Power management and sleep modes
System control and reset
WDT - Watchdog timer
Interrupts and programmable multilevel interrupt controller
PORT - I/O ports
TC - 16-bit timer/counters
AWeX - Advanced waveform extension
Hi-Res - High resolution extension
RTC - Real-time counter
USB - Universal serial bus interface
TWI - Two-wire serial interface
SPI - Serial peripheral interface
USART - Universal synchronous and asynchronous serial receiver and transmitter
IRCOM - Infrared communication module
AES and DES cryptographic engine
CRC - Cyclic redundancy check
LCD - Liquid Crystal Display controller
ADC - Analog-to-digital converter
AC - Analog comparator
IEEE 1149.1 JTAG interface
PDI - Program and debug interface
Memory programming
Peripheral address map
Register summary
Interrupt vector summary
Instruction set summary
8-bit Atmel XMEGA B Microcontroller
XMEGA B MANUAL
8291B- AVR-01/2013
8291B–AVR–01/2013

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Summary of Contents for Atmel XMEGA B

  • Page 1 ® Atmel XMEGA B microcontroller family. The Atmel AVR XMEGA B is a family of low- power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture with integrated LCD controller. The available Atmel AVR XMEGA B modules described in this manual are: Atmel AVR CPU ...
  • Page 2: About The Manual

    For example each port module (PORT) have unique name, such as PORTA, PORTB, etc. Register and bit names are unique within one module instance. For more details on applied use and code examples for peripherals and modules, refer to the Atmel AVR XMEGA specific application notes available from http://www.atmel.com/avr.
  • Page 3: Overview

    The Atmel AVR XMEGA B devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
  • Page 4 PE[0..7] Table 2-1 on page 5 a feature summary for the XMEGA B family is shown, split into one feature summary column for each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet for ordering codes and memory options.
  • Page 5 Table 2-1. XMEGA B feature summary overview. Feature Details / sub-family Total Pins, I/O Programmable I/O pins 64 - 128 64 - 128 Program memory (KB) 4 - 8 4 - 8 Boot memory (KB) 4 - 8 4 - 8...
  • Page 6 CRC-16 CRC-32 Segments Liquid Crystal Display Controller (LCD) Common terminals Resolution (bits) Analog to Digital Converter Sampling speed (kbps) (ADC) Input channels per ADC Conversion channels Analog Comparator (AC) Program and Debug Interface JTAG Boundary scan XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 7: Atmel Avr Cpu

    For a summary of all AVR instructions, refer to “Instruction Set Summary” on page 397. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 3-1. Block diagram of the AVR CPU architecture. XMEGA B [DATASHEET]...
  • Page 8: Alu - Arithmetic Logic Unit

    Multiplication of a signed integer with an unsigned integer  Multiplication of unsigned fractional numbers  Multiplication of signed fractional numbers  Multiplication of a signed fractional number with an unsigned one  A multiplication takes two CPU clock cycles. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 9: Program Flow

    In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 3-3. Single Cycle ALU Operation Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 10: Status Register

    Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 11 X-register, Y-register, and Z-register. The Z-register can also be used as an address pointer to read from and/or write to the flash program memory, signature rows, fuses, and lock bits. Figure 3-5. The X-, Y- and Z-registers Bit (individually) X-register Bit (X-register) Bit (individually) Y-register Bit (Y-register) Bit (individually) Z-register Bit (Z-register) XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 12: Ramp And Extended Indirect Registers

    This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB. Together, RAMPD and the operand will form a 24-bit address. Figure 3-7. The combined RAMPD + K register. Bit (Individually) RAMPD Bit (D-pointer) XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 13: Accessing 16-Bit Registers

    This bit must be written to one in the same oper- ation as the data are written. The protected change is immediately disabled if the CPU performs write operations to the I/O register or data memory or if the SPM, LPM, or SLEEP instruction is executed. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 14: Fuse Lock

    If this is done, it will not be possible to change the registers from the user software, and the fuse can only be reprogrammed using an external programmer. Details on this are described in the datasheet module where this feature is available. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 15: Register Descriptions

    These bits hold the MSB of the 24-bit address created by RAMPD and the 16-bit operand. Only the number of bits required to address the available data memory is implemented for each device. Unused bits will always read as zero. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 16 These bits hold the MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register. Only the number of bits required to address the available data and program memory is implemented for each device. Unused bits will always read as zero. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 17 3.14.8 SPH – Stack Pointer Register High +0x0E SP[15:8] Read/Write Initial Value Note: Refer to specific device datasheets for exact initial values.  Bit 7:0 – SP[15:8]: Stack Pointer Register High These bits hold the MSB of the 16-bit stack pointer (SP). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 18 The zero flag (Z) indicates a zero result in an arithmetic or logic operation. See “Instruction Set Description” for detailed information.  Bit 0 – C: Carry Flag The carry flag (C) indicates a carry in an arithmetic or logic operation. See “Instruction Set Description” for detailed information. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 19: Register Summary

    – – – – – +0x07 Reserved – – – – – – – – +0x08 RAMPD RAMPD[7:0] +0x09 RAMPX RAMPX[7:0] +0x0A RAMPY RAMPY[7:0] +0x0B RAMPZ RAMPZ[7:0] +0x0C EIND EIND[7:0] +0x0D SPL[7:0] +0x0E SPH[7:0] +0x0F SREG XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 20: Memories

    All XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 21 The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 22: Fuses And Lockbits

    Both fuses and lock bits are reprogrammable like the flash program memory. Data Memory The data memory contains the I/O memory, internal SRAM and optionally memory mapped EEPROM. The data memory is organized as one continuous memory section, as shown in Figure 4-2 on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 23: Internal Sram

    Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memories at the same time. As Figure 4-3 on page 24 shows, XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 24: Memory Timing

    4.11 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. XMEGA B [DATASHEET]...
  • Page 25: Jtag Disable

    I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 26: Register Description - Nvm Controller

    The DATA0, DATA1, and DATA registers represent the 24-bit value, DATA. This holds data during NVM read, write, and CRC access. +0x04 DATA[7:0] Read/Write Initial Value  Bit 7:0 – DATA[7:0]: Data Register Byte 0 This register gives the data value byte 0 when accessing NVM locations. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 27 Bit 0 – CMDEX: Command Execute Setting this bit will execute the command in the CMD register. This bit is protected by the configuration change protection (CCP) mechanism. Refer to “Configuration Change Protection” on page 14 for details on the CCP. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 28 NVMBUSY flag in the STATUS register is set to zerozero. Thus, the interrupt should not be enabled before triggering an NVM command, as the NVMBUSY flag won’t be set before the NVM command is triggered. The interrupt should be disabled in the interrupt handler. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 29 The FLOAD flag indicates that the temporary flash page buffer has been loaded with one or more data bytes. It remains set until an application, boot page write, or page buffer flush operation is executed. For more details, see “Flash and EEPROM Programming Sequences” on page 388. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 30: Register Descriptions - Fuses And Lock Bits

    These fuse bits are used to set the initial value of the watchdog timeout period. During reset, these fuse bits are automatically written to the PER bits in the watchdog control register. .RRefer to “CTRL – Control register” on page 117 for details. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 31 These fuse bits set the BOD operation mode in all sleep modes except idle mode. For details on the BOD and BOD operation modes, refer to “Brownout Detection” on page 109. Table 4-3. BOD operation modes in sleep modes. BODPD[1:0] Description Reserved BOD enabled in sampled mode BOD enabled continuously BOD disabled XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 32 When the JTAG interface is disabled, all access through JTAG is prohibited, and the device can be accessed using only the program and debug interface (PDI). The JTAGEN fuse is available only on devices with JTAG interface. A reset is required before this bit will be read correctly after it is changed. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 33 Bit 2:0 – BODLEVEL[2:0]: Brownout Detection Voltage Level These fuse bits sets the BOD voltage level. R ,,evenor.Refer to “Reset System” on page 107 for details. For BOD level nominal values, see Table 9-2 on page 110. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 34 (E)LPM executing from the boot loader section is not allowed to read from the application section. RWLOCK If the interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 35 EEPROM are disabled for the programming interface. RWLOCK The lock bits and fuses are locked for read and write from the programming interface. Note: Program the Fuse Bits and Boot Lock Bits before programming the Lock Bits. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 36: Register Description - Production Signature Row

    This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is performed during production testing of the device. During reset, this value is automatically loaded into calibration register B for the 32MHz DFLL. Refer to “CALB – Calibration register B” on page 94 for more details. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 37 This byte contains byte 1 of the lot number for the device. 4.16.8 LOTNUM2 – Lot Number register 2 +0x0A LOTNUM2[7:0] Read/Write Initial Value  Bit 7:0 – LOTNUM2[7:0]: Lot Number Byte 2 This byte contains byte 2 of the lot number for the device. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 38 WAFNUM[7:0] Read/Write Initial Value  Bit 7:0 – WAFNUM[7:0]: Wafer Number This byte contains the wafer number for each device. Together with the lot number and wafer coordinates, this gives a serial number for the device. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 39 This byte contains byte 0 of wafer coordinate Y for the device. 4.16.16 COORDY1 – Wafer Coordinate Y register 1 +0x15 COORDY1[7:0] Read/Write Initial Value  Bit 7:0 – COORDY1[7:0]: Wafer Coordinate Y Byte 1 This byte contains byte 1 of wafer coordinate Y for the device. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 40 +0x20 ADCACAL0[7:0] Read/Write Initial Value  Bit 7:0 – ADCACAL0[7:0]: ADCA Calibration Byte 0 This byte contains byte 0 of the ADCA calibration data, and must be loaded into the ADCA CALL register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 41 The measurement is done in production testing at 85C, and can be used for single- or multi-point temperature sensor calibration. +0x2E TEMPSENSE0[7:0] Read/Write Initial Value  Bit 7:0 – TEMPSENSE0[7:0]: Temperature Sensor Calibration Byte 0 This byte contains the byte 0 of the temperature measurement. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 42: Register Description - General Purpose I/O Memory

     Bit 7:0 – DEVID0[7:0]: Device ID Byte 0 Byte 0 of the device ID. This byte will always be read as 0x1E. This indicates that the device is manufactured by Atmel. 4.18.2 DEVID1 – Device ID register 1 +0x01...
  • Page 43  Bit 0 – JTAGD: JTAG Disable Setting this bit will disable the JTAG interface. This bit is protected by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 44 CH0MUX, CH0CTRL, CH1MUX, CH1CTRL, CH2MUX, CH2CTRL, CH3MUX, and CH3CTRL. This bit is protected by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 45 Setting this bit will lock all registers in the AWEXC module for Timer/Counter C0 foragainst further modification. This bit is protected by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 46: Register Summary - Nvm Controller

    – – – – +0x04 FUSEBYTE – – – RSTDISBL STARTUPTIME[1:0] WDLOCK JTAGEN +0x05 FUSEBYTE – – BODACT[1:0] EESAVE BODLEVEL[2:0] +0x06 Reserved – – – – – – – – +0x07 LOCKBITS BLBB[1:0] BLBA[1:0] BLBAT[1:0] LB[1:0] XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 47: Register Summary - Production Signature Row

    – – – – – – +0x3C Reserved – – – – – – – – +0x3D Reserved – – – – – – – – +0x3E Reserved – – – – – – – – XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 48: Register Summary - General Purpose I/O Registers

    – +0x0B Reserved – – – – – – – – 4.24 Interrupt Vector Summary - NVM Controller Offset Source Interrupt Description 0x00 EE_vect Nonvolatile memory EEPROM interrupt vector 0x02 SPM_vect Nonvolatile memory SPM interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 49: Dmac - Direct Memory Access Controller

    DMA controller detects an error on a DMA channel. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 50: Dma Transaction

    SRAM, I/O memory, EEPROM or the external bus interface. For more details on memory access bus arbitration, refer to “Data Memory” on page Figure 5-2. DMA transaction. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 51: Transfer Triggers

    To avoid unnecessary bus loading when doing data transfer between memories with different access timing (for example, I/O register and external memory), the DMA controller has a four-byte buffer. Two bytes will be read from the source address and written to this buffer before a write to the destination is started. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 52: Error Detection

    If repeat is not enabled, the transaction complete flag is set at the end of the block transfer. If unlimited repeat is enabled, the transaction complete flag is also set at the end of each block transfer. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 53: Register Description - Dma Controller

    – CH1TRNFIF CH0TRNFIF Read/Write Initial Value  Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 54 CPU. Byte 1 of the 16/24-bit register is stored when byte 0 is read by the CPU. This register can also be read and written from the user software. Reading and writing 16- and 24-bit registers requires special attention. For details, refer to “Accessing 16-bit Registers” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 55: Register Description - Dma Channel

    Bit 2 – SINGLE: Single-Shot Data transfer Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 56 When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This flag is automatically cleared when the DMA channel is disabled, when the channel transaction complete interrupt flag is set or when the channel error interrupt flag is set. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 57 BLOCK of each block transfer. DMA source address register is reloaded with initial value at end BURST of each burst transfer. DMA source address register is reloaded with initial value at end TRANSACTION of each transaction. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 58 These bits decide the DMA channel destination address mode according to Table 5-7. These bits cannot be changed if the channel is busy. Table 5-7. DMA channel destination address mode settings DESTDIR[1:0] Group Configuration Description FIXED Fixed Increment Decrement Reserved XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 59 USART D0 DMA triggers base value 0x80 TCE0 Timer/counter E0 DMA triggers base value 0x8B USARTE0 USART E0 DMA triggers base value 0xA0 TCF0 Timer/counter F0 DMA triggers base value 0xAB USARTF0 USART F0 DMA triggers base value XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 60 These bits hold the LSB of the 16-bit block transfer count. The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trigger, DMA will be doing 0xFFFF transfers. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 61 SRCDIR bits in “ADDRCTRL – Address Control register” on page +0x08 SRCADDR[7:0] Read/Write Initial Value  Bit 7:0 – SRCADDR[7:0]: Channel Source Address byte 0 These bits hold byte 0 of the 24-bit source address. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 62 DESTDIR bits in “ADDRCTRL – Address Control register” on page +0x0C DESTADDR[7:0] Read/Write Initial Value  Bit 7:0 – DESTADDR[7:0]: Channel Destination Address byte 0 These bits hold byte 0 of the 24-bit source address. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 63 Reading and writing 24-bit values require special attention. For details, refer to “Accessing 24- and 32-bit Registers” on page +0x0E DESTADDR[23:16] Read/Write Initial Value  Bit 7:0 – DESTADDR[23:16]: Channel Destination Address byte 2 These bits hold byte 2 of the 24-bit source address. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 64: Register Summary - Dma Controller

    DESTADDR[23:16] +0x0F Reserved – – – – – – – – 5.17 DMA Interrupt Vector Summary Offset Source Interrupt Description 0x00 CH0_vect DMA controller channel 0 interrupt vector 0x02 CH1_vect DMA controller channel 1 interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 65: Event System

    I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM) and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also be generated from software and the peripheral clock. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 66: Events

    The peripheral using the event is called the event user, and the action that is triggered is called the event action. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 67 Software-generated events last for one clock cycle and will overwrite events from other event generators on that event channel during that clock cycle. Table 6-1 on page 68 shows the different events, how they can be manually generated, and how they are decoded. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 68: Event Routing Network

    For each peripheral, it is selectable if and how incoming events should trigger event actions. Details on configurations can be found in the datasheet for each peripheral. The event routing network is shown in Figure 6-3 on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 69: Event Timing

    An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise stated, an event lasts for one peripheral clock cycle. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 70: Filtering

    When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads QDPH90, the rotation is defined as negative or reverse. The concatenation of the two phase signals is called the quadrature state or the phase state. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 71 If the count register is different from BOTTOM when the index is recognized, the timer/counter error flag is set. Similarly, the error flag is set if the position counter passes BOTTOM without the recognition of the index. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 72: Register Description

    USB setup on CH3 0000 (Reserved) 0000 (Reserved) 0001 ACA_CH0 ACA channel 0 0001 ACA_CH1 ACA channel 1 0001 ACA_WIN ACA window 0001 (Reserved) 0001 (Reserved) 0001 (Reserved) 0010 ADCA_CH0 ADCA 0010 (Reserved) 0010 (Reserved) 0010 (Reserved) XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 73 Capture or compare B (x = C, D, E or F) (n= 0 or 1) TCxn_CCC Capture or compare C (x = C, D, E or F) (n= 0) TCxn_CCD Capture or compare D (x = C, D, E or F) (n= 0) XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 74 DIGFILT. Table 6-6. Digital filter coefficient values . DIGFILT[2:0] Group Configuration Description 1SAMPLE One sample 2SAMPLES Two samples 3SAMPLES Three samples XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 75 This register contains the data value when manually generating a data event. This register must be written before the STROBE register. For details, See ”STROBE – Strobe register” on page 75. +0x11 DATA[7:0] Read/Write Initial Value XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 76: Register Summary

    +0x0D Reserved – – – – – – – – +0x0E Reserved – – – – – – – – +0x0F Reserved – – – – – – – – +0x10 STROBE STROBE[7:0] +0x11 DATA DATA[7:0] XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 77: System Clock And Clock Options

    XMEGA family of devices. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in “Power Management and Sleep Modes” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 78 Prescaler Timer Brown-out Detector System Clock Multiplexer RTCSRC (SCLKSEL) USBSRC PLLSRC XOSCSEL 0.4 – 16 MHz 32 kHz 32.768 kHz 32.768 kHz 32 MHz 2 MHz Int. ULP Int. OSC TOSC XTAL Int. Osc Int. Osc XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 79: Clock Distribution

    The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 80 To drive the device from an external clock source, XTAL1 pin or any pin of PORTC can be used. XTAL1 must be driven as shown in Figure 7-3 on page 80. In this mode, XTAL2 can be used as a general I/O pin. Figure 7-3. External clock drive configuration. General Purpose XTAL2 External Clock XTAL1 Signal XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 81: System Clock Selection And Prescalers

    The system clock selection and prescaler registers are protected by the configuration change protection mechanism, employing a timed write procedure for changing the system clock and prescaler settings. For details, refer to “Configuration Change Protection” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 82: Pll With 1X-31X Multiplication Factor

     USB start of frame  The DFLLs divide the oscillator reference clock by 32 to use a 1.024kHz reference. The reference clock is individually selected for each DFLL, as shown on Figure 7-6 on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 83 DFLL will decrement or increment its calibration register value by one to adjust the oscillator frequency. The oscillator is considered running too fast or too slow when the error is more than a half calibration step size. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 84: Pll And External Clock Source Failure Monitor

    The PLL and external clock source failure monitor settings are protected by the configuration change protection mechanism, employing a timed write procedure for changing the settings. For details, refer to “Configuration Change Protection” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 85: Register Description - Clock

    – PSADIV[4:0] PSBCDIV Read/Write Initial Value  Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 86 Table 7-3. Prescaler B and C division factors. PSBCDIV[1:0] Group configuration Prescaler B division Prescaler C division No division No division No division Divide by 2 Divide by 4 No division Divide by 2 Divide by 2 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 87 Reserved — Reserved TOSC32 32.768kHz from 32.768kHz crystal oscillator on TOSC RCOSC32 32.768kHz from 32.768kHz internal oscillator EXTCLK External clock from TOSC1 Note: The LCD will always use the non-prescaled 32kHz oscillator output as clock source. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 88 The 32MHz internal oscillator must be calibrated to 48MHz before selecting this as source for the USB device module. Refer to “DFLL 2MHz and DFLL 32MHz” on page  Bit 0 – USBSEN: USB Clock Source Enable Setting this bit enables the selected clock source for the USB device module. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 89: Register Description - Oscillator

    This flag is set when the 32.768kHz internal oscillator is stable and is ready to be used as the system clock source.  Bit 1 – RC32MRDY: 32MHz Internal Oscillator Ready This flag is set when the 32MHz internal oscillator is stable and is ready to be used as the system clock source. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 90 Table 7-8 on page 91 for crystal selections. If an external clock or external oscillator is selected as the source for the system clock, see “CTRL – Control register” on page 89. This configuration cannot be changed. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 91 Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when XOSCFDIF is set. This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on page 14 for details. Once enabled, failure detection can only be disabled by a reset. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 92 – RC32MCREF[1:0] RC2MCREF Read/Write Initial Value  Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 93: Register Description - Dfll32M/Dfll2M

    When the DFLL is disabled, the calibration registers can be written by software for manual run-time calibration of the oscillator. The oscillators will also be calibrated according to the calibration value in these registers when the DFLL is disabled. +0x02 – CALA[6:0] Read/Write Initial Value XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 94 The bits cannot be written when the DFLL is enabled. When calibrating to a frequency different from the default, the CALA bits should be set to a middle value to maximize the range for the DFLL. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 95 Table 7-11. Nominal DFLL32M COMP values for different output frequencies. Oscillator frequency (MHz) COMP value (Clk = 1.024kHz) RCnCREF 30.0 0x7270 32.0 0x7A12 34.0 0x81B3 36.0 0x8954 38.0 0x90F5 40.0 0x9896 42.0 0xA037 44.0 0xA7D8 46.0 0xAF79 48.0 0xB71B 50.0 0xBEBC 52.0 0xC65D 54.0 0xCDFE XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 96: Register Summary - Clock

    +0x05 COMP1 COMP[7:0] +0x06 COMP2 COMP[15:8] +0x07 Reserved – – – – – – – – 7.15 Oscillator Failure Interrupt Vector Summary Offset Source Interrupt Description 0x00 OSCF_vect PLL and external oscillator failure interrupt vector (NMI) XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 97: Power Management And Sleep Modes

    After wake-up, the CPU is halted for four cycles before execution starts. Table 8-1 on page 98 shows the different sleep modes and the active clock domains, oscillators, and wake-up sources. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 98 8.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC/LCD clocks are stopped. This reduces the wake-up time. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 99: Power Reduction Registers

    In sleep modes where the Peripheral Clock (Clk ) is stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 100 If the On-chip debug system is enabled and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 101: Register Description - Sleep

    – EVSYS Read/Write Initial Value  Bit 7 – LCD: LCD Module Setting this bit stops the clock to the LCD module. When the bit is cleared the peripheral should be reinitialized to ensure proper operation. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 102 USART0 HIRES +0x05/+0x06 Read/Write Initial Value  Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 103 Setting this bit stops the clock to timer/counter 1. When this bit is cleared, the peripheral will continue like before the shut down.  Bit 0 – TC0: Timer/Counter 0 Setting this bit stops the clock to timer/counter 0. When this bit is cleared, the peripheral will continue like before the shut down. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 104: Register Summary - Sleep

    – – – +0x02 PRPB – – – – – – +0x03 PRPC – – USART0 HIRES +0x04 Reserved – – – – – – – – +0x05 PRPE – – – USART0 – – – XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 105: Reset System

    The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. An overview of the reset system is shown in Figure 9-1 on page 106. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 106: Reset Sequence

    SUT[1:0] Number of 1kHz ULP Oscillator Clock Cycles Recommended Usage 64K Clk + 24 Clk Stable frequency at startup 4K Clk + 24 Clk Slowly rising power Reserved 24 Clk Fast rising power or BOD enabled XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 107: Reset Sources

    BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. When the BOD is enabled and V decreases to a value below the trigger level (V Figure 9-4), the brownout reset BOT- is immediately activated. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 108 Sampled: In this mode, the BOD circuit will sample the V level with a period identical to that of the 1kHz output  from the ultra low power (ULP) internal oscillator. Between each sample, the BOD is turned off. This mode will XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 109 The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 110 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 111: Register Description

    Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.  Bit 0 – SWRST: Software Reset XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 112: Register Summary

    Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 STATUS – – PDIRF WDRF BORF EXTRF PORF +0x01 CTRL – – – – – – – SWRST XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 113: Wdt - Watchdog Timer

    WDT is reset by the WDR instruction. The default timeout period is controlled by fuses. Normal mode operation is illustrated in Figure 10-1 on page 113. Figure 10-1. Normal mode operation. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 114: Window Mode Operation

    WDT cannot be disabled from software. After system reset, the WDT will resume at the configured operation. When the WDT lock fuse is programmed, the window mode timeout period cannot be changed, but the window mode itself can still be enabled or disabled. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 115: Registers Description

    0100 128CLK 0.128s 0101 256CLK 0.256s 0110 512CLK 0.512s 0111 1KCLK 1.0s 1000 2KCLK 2.0s 1001 4KCLK 4.0s 1010 8KCLK 8.0s 1011 – Reserved 1100 – Reserved 1101 – Reserved 1110 – Reserved 1111 – Reserved XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 116 WPER[3:0] Group Configuration Typical Closed Window Periods 0000 8CLK 0001 16CLK 16ms 0010 32CLK 32ms 0011 64CLK 64ms 0100 128CLK 0.128s 0101 256CLK 0.256s 0110 512CLK 0.512s 0111 1KCLK 1.0s 1000 2KCLK 2.0s 1001 4KCLK 4.0s XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 117: Register Summary

    Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – PER[3:0] ENABLE +0x01 WINCTRL – – WPER[3:0] WCEN +0x02 STATUS – – – – – – – SYNCBUSY XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 118: Interrupts And Programmable Multilevel Interrupt Controller

    PMIC to the state it had before entering the interrupt. The status register (SREG) is not saved automatically upon an interrupt request. The RET (subroutine return) instruction cannot be used when returning from the interrupt handler routine, as this will not return the PMIC to its correct state. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 119: Interrupts

    After the program counter is pushed on the stack, the program vector for the interrupt is executed. The jump to the interrupt handler takes three clock cycles. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 120 A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the program counter. During these clock cycles, the program counter is popped from the stack and the stack pointer is incremented. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 121: Interrupt Level

    Refer to the interrupt vector summary of each module and peripheral in this manual for a list of interrupts and their corresponding offset address within the different modules and peripherals. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 122 PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the interrupt vector address for the last acknowledged low-level interrupt will have the lowest priority the next time one or more interrupts from the low level is requested. Figure 11-4. Round-robin scheduling. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 123: Interrupt Vector Locations

    Boot section or vice versa. Table 11-2. Reset and interrupt vectors placement BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 0x0000 0x0002 0x0000 Boot Reset Address + 0x0002 Boot Reset Address 0x0002 Boot Reset Address Boot Reset Address + 0x0002 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 124: Register Description

    The register is accessible from software to change the priority queue. This register is not reinitialized to its initial value if round-robing scheduling is disabled, and so if default static priority is needed, the register must be written to zero. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 125: Register Summary

    Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 STATUS NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX +0x01 INTPRI INTPRI[7:0] +0x02 CTRL RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 126: I/O Ports

    USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. Figure 12-1 on page 127 shows the I/O pin functionality and the registers that are available for controlling a pin. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 127: I/O Pin Use And Configuration

    It is also possible to enable inverted input and output for a pin. A totem-pole output has four possible pull configurations: totem-pole (push-pull), pull-down, pull-up, and bus-keeper. The bus-keeper is active in both directions. This is to avoid oscillation when disabling the output. The totem-pole XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 128 In this mode, the configuration is the same as for totem-pole mode, expect the pin is configured with an internal pull-down resistor when set as input. Figure 12-3. I/O pin configuration - Totem-pole with pull-down (on input). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 129 If the last logic level on the pin/bus was 0, the bus-keeper will use the internal pull resistor to keep the bus low. Figure 12-5. I/O pin configuration - Totem-pole with bus-keeper. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 130 When the OUT register is set to one, the pin is released allowing the pin to be pulled high with the internal or an external pull-resistor. If internal pull-up is used, this is also active if the pin is set as input. Figure 12-7. Output configuration - Wired-AND with optional pull-up. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 131: Reading The Pin Value

    The maximum and minimum propagation delays are denoted as t and t , respectively. pd,max pd,min Figure 12-8. Synchronization when reading a pin value. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 132: Input Sense Configuration

    Table 12-1, Table 12-2, and Table 12-3 on page 133 summarize when interrupts can be triggered for the various input sense configurations. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 133: Port Event

    For events to be generated on a low level, the pin configuration must be set to inverted I/O. Table 12-4. Event sense support Sense Settings Signal event Data event Rising edge Rising edge Pin value Falling edge Falling edge Pin value Both edge Any edge Pin value Low level Pin value Pin value XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 134: Alternate Port Functions

    Pull Direction PINnCTRL Digital Input Disable (DID) DID Override Value DID Override Enable Wired AND/OR Inverted I/O OUTn OUT Override Value OUT Override Enable DIRn DIR Override Value DIR Override Enable Synchronizer Digital Input Pin Analog Input/Output XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 135: Clock And Event Output

    This enables the use of I/O memory-specific instructions, such as bit-manipulation instructions, on a port register that normally resides in the extended I/O memory space. There are four virtual ports, and so four ports can be mapped at the same time. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 136: Register Descriptions - Ports

    This register can be used instead of a read-modify-write to set individual pins as input. Writing a one to a bit will clear the corresponding bit in the DIR register. Reading this register will return the value of the DIR register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 137 This register can be used instead of a read-modify-write to set the output value of individual pins to zero. Writing a one to a bit will clear the corresponding bit in the OUT register. Reading this register will return the value in the OUT register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 138  Bit 3:2/1:0 – INTnLVL[1:0]: Interrupt n Level These bits enable port interrupt n and select the interrupt level as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 139 The INTnIF flag is set when a pin change/state matches the pin's input sense configuration, and the pin is set as source for port interrupt n. Writing a one to this flag's bit location will clear the flag. For enabling and executing the interrupt, refer to the interrupt level description. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 140 Setting this bit will move the location of OC0A from Px0 to Px4. If this bit is set and PWM from both timer/counter 0 and timer/counter 1 is enabled, the resulting PWM will be an OR-modulation between the two PWM outputs. See Figure 12- Figure 12-11.I/O timer/counter. OC0A OC1A XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 141 If the input buffer is not disabled, the input cannot be read in the IN register. Table 12-6. Input/sense configuration. ISC[2:0] Group Configuration Description BOTHEDGES Sense both edges RISING Sense rising edge FALLING Sense falling edge LEVEL Sense low level XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 142 A low-level pin value will not generate events, and a high-level pin value will continuously generate events. Only PORTA - PORTF support the input buffer disable option. If the pin is used for analog functionality, such as AC or ADC, it is recommended to configure the pin to INPUT_DISABLE. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 143: Register Descriptions - Port Configuration

    These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 12-7 on page 144 for configuration. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 144 These bits decide which port event channel 0 from the event system will be output to. Pin 7 on the selected port is the default used, and the CLKOUT bits must be set differently from those of EVOUT. The port pin must be configured as output for the event to be available on the pin. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 145 The port pin must be configured as output for the clock to be available on the pin. Table 12-10 shows the possible configurations. Table 12-10. Clock output port configurations. CLKOUT[1:0] Group Configuration Description Clock output disabled Clock output on PORTC Clock output on PORTD Clock output on PORTE XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 146 Event channel 2 output to pin Event channel 3 output to pin Event channel 4 output to pin Event channel 5 output to pin Event channel 6 output to pin Event channel 7 output to pin XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 147: Register Descriptions - Virtual Port

    A or VPCTRLB, virtual port-map control register A, decides the value in the register. When a port is mapped as virtual, accessing this register is identical to accessing the actual IN register for the port. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 148 The configuration of VPCTRLA, virtual port-map control register A, or VPCTRLB, Virtual Port-map Control Register B, decides which flags are mapped. When a port is mapped as virtual, accessing this register is identical to accessing the actual INTFLAGS register for the port. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 149: Register Summary - Ports

    12.17 Register Summary – Virtual Ports Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 DIR[7:0] +0x01 OUT[7:0] +0x02 IN[7:0] +0x03 INTFLAGS – – – – – – INT1IF INT0IF XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 150: Interrupt Vector Summary - Ports

    12.18 Interrupt Vector Summary – Ports Offset Source Interrupt Description 0x00 INT0_vect Port interrupt vector 0 offset 0x02 INT1_vect Port interrupt vector 1 offset XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 151: Tc0/1 - 16-Bit Timer/Counter Type 0 And 1

    13.2 Overview Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
  • Page 152 “counter” is used when the clock control is handled externally (e.g. counting external events). When used for compare operations, the CC channels are referred to as “compare channels.” When used for capture operations, the CC channels are referred to as “capture channels.” XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 153: Block Diagram

    A prescaled peripheral clock and events from the event system can be used to control the counter. The event system is also used as a source to the input capture. Combined with the quadrature decoding functionality in the event system (QDEC), the timer/counter can be used for quadrature decoding. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 154: Clock And Event Sources

    When the period register and CC channels are used for a compare operation, the buffer valid flag is set when data is written to the buffer register and cleared on an UPDATE condition. This is shown for a compare register in Figure 13-4 on page 155. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 155: Counter Operation

    BOTTOM. When up-counting and TOP is reached, the counter will be set to zero when the next clock is given. When down-counting, the counter is reloaded with the period register value when BOTTOM is reached. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 156 Figure 13-7 on page 156. Figure 13-7. Changing the period without buffering. Counter Wraparound "update" "write" BOTTOM New TOP written to New TOP written to PER that is higher PER that is lower than current CNT than current CNT XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 157: Capture Channel

    CC channels, if configured. For example, setting the event source select to event channel 2 results in CC channel A being triggered by event channel 2, CC channel B triggered by event channel 3, and so on. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 158 This enables the timer/counter to measure the period or frequency of a signal directly. The capture result will be the time (T) from the previous timer/counter restart until the event occurred. This can be used to calculate the frequency (f) of the signal: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 159 Figure 13-13 on page 159 shows and example where the pulse width is measured twice for an external signal. Figure 13-13.Pulse width capture of an external signal. Pulsewitdh (t external signal events "capture" BOTTOM XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 160: Compare Channel

    For frequency generation the period time (T) is controlled by the CCA register instead of PER. The waveform generation (WG) output is toggled on each compare match between the CNT and CCA registers, as shown in Figure 13-14 on page 161. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 161   -------------------------------- - 2   PWM_SS The single-slope PWM frequency (f ) depends on the period setting (PER) and the peripheral clock frequency PWM_SS (fclk ), and can be calculated by the following equation: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 162 To make the waveform generation available on the port pins, the corresponding port pin direction must be set as output. The timer/counter will override the port pin values when the CC channel is enabled (CCENx) and a waveform generation mode is selected. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 163: Interrupts And Events

    The software can force a restart of the current waveform period by issuing a restart command. In this case the counter, direction, and all compare outputs are set to zero. A reset command will set all timer/counter registers to their initial values. A reset can be given only when the timer/counter is not running (OFF). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 164: Register Description

    Setting these bits in the FRQ or PWM waveform generation mode of operation will override the port output register for the corresponding OCn output pin. When input capture operation is selected, the CCxEN bits enable the capture operation for the corresponding CC channel. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 165 These bits allow direct access to the waveform generator's output compare value when the timer/counter is set in the OFF state. This is used to set or clear the WG output value when the timer/counter is not running. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 166 (n+3)%8 will be the event channel source for CC channel B, C, and D. Table 13-6. Timer event source selection EVSEL[3:0] Group Configuration Event Source 0000 None 0001 – Reserved 0010 – Reserved 0011 – Reserved XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 167 – ERRINTLVL[1:0] OVFINTLVL[1:0] Read/Write Initial Value  Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 168 These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.  Bit 3:2 – CMD[1:0]: Command These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 169 Note that when input capture operation is used, this bit is set on a capture event and cleared if the corresponding CCxIF is cleared.  Bit 0 – PERBV: Period Buffer Valid This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared on an UPDATE condition. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 170 OVFIF is automatically cleared when the corresponding interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. OVFIF can also be used for requesting a DMA transfer. A DMA write access of CNT, PER, or PERBUF will then clear the OVFIF bit. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 171 The PERH and PERL register pair represents the 16-bit value, PER. PER contains the 16-bit TOP value in the timer/counter. +0x26 PER[7:0] Read/Write Initial Value  Bit 7:0 – PER[7:0]: Period low byte These bits hold the LSB of the 16-bit period register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 172 These bits hold the LSB of the 16-bit compare or capture register. 13.12.17CCxH – Compare or Capture x register High CCx[15:8] Read/Write Initial Value  Bit 7:0 – CCx[15:8]: Compare or Capture x high byte These bits hold the MSB of the 16-bit compare or capture register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 173 (CCx). Accessing any of these registers using the CPU or DMA will affect the corresponding CCxBV status bit. CCxBUFx[7:0] Read/Write Initial Value  Bit 7:0 – CCxBUF[7:0]: Compare or Capture Buffer low byte These bits hold the LSB of the 16-bit compare or capture buffer register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 174 13.12.21CCxBUFH – Compare or Capture x Buffer register High CCxBUF[15:8] Read/Write Initial Value  Bit 7:0 – CCxBUF[15:8]: Compare or Capture Buffer high byte These bits hold the MSB of the 16-bit compare or capture buffer register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 175: Register Summary

    Timer/counter compare or capture channel B interrupt vector offset 0x08 CCC_vect Timer/counter compare or capture channel C interrupt vector offset 0x0A CCD_vect Timer/counter compare or capture channel D interrupt vector offset Note: Available only on timer/counters with four compare or capture channels. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 176: Tc2 - 16-Bit Timer/Counter Type 2

    The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as either type 0 or type 2. A detailed block diagram of the timer/counter 2 showing the low-byte (L) and high-byte (H) timer/counter register split and compare modules is shown in Figure 14-1 on page 177. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 177: Block Diagram

    The timer/counter can be clocked from the peripheral clock (clk ) and from the event system. Figure 14-2 shows the clock and event selection. Figure 14-2. Clock selection. Common Event events {0,...,15} Prescaler System event channels {1,2,4,8,64,256,1024} CLKSEL XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 178: Counter Operation

    For the low-byte timer/counter, the match will set the compare channel's interrupt flag at the next timer clock cycle, and the event and optional interrupt is generated. The high-byte timer/counter does not have compare interrupt/event. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 179 CMP channels A to D will override the output value (OUTxn) of port pins 0 to 3 on the corresponding port pins (Pxn). For the high-byte timer/counter, CMP channels E to H will override port pins 4 to 7. Enabling inverted I/O on the port pin (INVENxn) inverts the corresponding WG output. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 180: Interrupts And Events

    The software can force a restart of the current waveform period by issuing a restart command. In this case the counter, direction, and all compare outputs are set to zero. A reset command will set all timer/counter registers to their initial values. A reset can only be given when the timer/counter is not running (OFF). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 181: Register Description

    LCMPENC LCMPENB LCMPENA Read/Write Initial Value  Bit 7:0 – HCMPENx/LCMPENx: High/Low Byte Compare Enable x Setting these bits will enable the compare output and override the port output register for the corresponding OCn output pin. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 182 Timer/counter is set to normal mode (timer/counter type 0) Upper byte of the counter (HCNT) will be set to zero after each counter BYTEMODE clock. Timer/counter is split into two eight-bit timer/counters (timer/counter type SPLITMODE — Reserved XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 183 Bit 3:2 – CMD[1:0]: Timer/Counter Command These command bits are used for software control of timer/counter update, restart, and reset. The command bits are always read as zero. The CMD bits must be used together with CMDEN. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 184 Bit 0 – LUNFIF: Low-byte Timer Underflow Interrupt Flag LUNFIF is set on a BOTTOM (underflow) condition. This flag is automatically cleared when the corresponding interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 185 Bit 7:0 – LPER[7:0] LPER contains the eight-bit period value for the low-byte timer/counter. 14.10.12HPER – High-byte Period register +0x26 HPER[7:0] Read/Write Initial Value  Bit 7:0 – HPER[7:0] HPER contains the eight-bit period for the high-byte timer/counter. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 186 Bit 7:0 – HCMPx[7:0], x=[A, B, C, D] HCMPx contains the eight-bit compare value for the high-byte timer/counter. These registers are all continuously compared to the counter value. Normally the outputs from the comparators are then used for generating waveforms. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 187: Register Summary

    Low-byte Timer/counter compare channel A interrupt vector offset LCMPB_vect Low-byte Timer/counter compare channel B interrupt vector offset LCMPC_vect Low-byte Timer/counter compare channel C interrupt vector offset 0x0A LCMPD_vect Low-byte Timer/counter compare channel D interrupt vector offset XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 188: Awex - Advanced Waveform Extension

    AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead- XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 189: Port Override

    When the dead-time enable (DTIENx) bit is set, the timer/counter extension takes control over the pin pair for the corresponding channel. Given this condition, the output override enable (OOE) bits take control over the CCxEN bits. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 190: Dead-Time Insertion

    The DTI unit consists of four equal dead-time generators, one for each compare channel in timer/counter 0. Figure 15-3 on page 191 shows the block diagram of one DTI generator. The four channels have a common register that controls the XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 191: Pattern Generation

    A block diagram of the pattern generator is shown in “Pattern generator block diagram.” on page 192. For each port pin where the corresponding OOE bit is set, the multiplexer will output the waveform from CCA. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 192: Fault Protection

    In cycle-by-cycle mode the waveform output will remain in the fault state until the fault condition is no longer active.  When this condition is met, the waveform output will return to normal operation at the next UPDATE condition. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 193 UPDATE condition after exit from break, while in latched mode, the fault condition flag must be cleared in software before the output will be restored. This feature guarantees that the output waveform enters a safe state during a break. It is possible to disable this feature. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 194: Register Description

    ORed together, allowing multiple sources to be used for fault detection at the same time. When a fault is detected, the fault detect flag (FDF) is set and the fault detect action (FDACT) will be performed. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 195 15-1, when a fault condition is detected. Table 15-1. Fault action. FDACT[1:0] Group Configuration Description NONE None (fault protection disabled) – Reserved – Reserved Clear all direction (DIR) bits which correspond to the enabled DTI CLEARDIR channel(s); i.e., tri-state the outputs XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 196 DTBOTHBUF[7:0] Read/Write Initial Value  Bit 7:0 – DTBOTHBUF: Dead-time Both Sides Buffer Writing to this memory location will update the DTHSBUF and DTLSBUF registers at the same time (i.e., at the same I/O write access). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 197 Bit 7:0 – DTHSBUF: Dead-time High Side Buffer This register is the buffer for the DTHS register. If double buffering is used, valid content in this register is copied to the DTHS register on an UPDATE condition. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 198: Register Summary

    – – – DTBHSV DTBLSV +0x05 Reserved – – – – – – – – +0x06 DTBOTH DTBOTH[7:0] +0x07 DTBOTHBUF DTBOTHBUF[7:0] +0x08 DTLS DTLS[7:0] +0x09 DTHS DTHS[7:0] +0x0A DTLSBUF DTLSBUF[7:0] +0x0B DTHSBUF DTHSBUF[7:0] +0x0C OUTOVEN OUTOVEN[7:0] XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 199: Hi-Res - High-Resolution Extension

    The extra resolution is achieved by counting on both edges of the peripheral 4x clock. The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than four will have no visible output. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 200: Register Description

    Timer/counter 0 Timer/counter 1 Both timer/counters 16.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRLA – – – – – HRPLUS HREN[1:0] XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 201: Rtc - Real-Time Counter

    Figure 17-1. Real-time counter overview. External Clock TOSC1 32.768kHz Crystal Osc TOSC2 32.768kHz Int. Osc 32kHz int ULP (DIV32) RTCSRC TOP/ Overflow 10-bit prescaler ”match”/ Compare COMP XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 202 If the period register is one, events will be generated only for every second overflow or compare match. When the period register is equal to or above two, events will trigger at every overflow or compare match, just as the interrupt request. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 203: Register Descriptions

    Bit 0 – SYNCBUSY: Synchronization Busy Flag This flag is set when the CNT, CTRL, PER, or COMP register is busy synchronizing between the RTC clock and system clock domains. THis flag is automatically cleared when the synchronisation is complete XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 204 This flag is set on the next count after an overflow condition occurs. It is cleared automatically when the RTC overflow interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 205 These bits hold the LSB of the 16-bit real-time counter value. 17.3.7 CNTH – Counter Register High +0x09 CNT[15:8] Read/Write Initial Value  Bit 7:0 – CNT[15:8]: Counter Value high byte These bits hold the MSB of the 16-bit real-time counter value. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 206 If the COMP value is higher than the PER value, no RTC compare match interrupt requests or events will ever be generated. +0x0C COMP[7:0] Read/Write Initial Value  Bit 7:0 – COMP[7:0]: Compare value low byte These bits hold the LSB of the 16-bit RTC compare value. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 207 17.3.11 COMPH – Compare register High +0x0D COMP[15:8] Read/Write Initial Value  Bit 7:0 – COMP[15:8]: Compare value high byte These bits hold the MSB of the 16-bit RTC compare value. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 208: Register Summary

    CNT[15:8] +0x0A PERL PER[7:0] +0x0B PERH PER[15:8] +0x0C COMPL COMP[7:0] +0x0D COMPH COMP[15:8] 17.5 Interrupt Vector Summary Offset Source Interrupt Description 0x00 OVF_vect Real-time counter overflow interrupt vector 0x02 COMP_vect Real-time counter compare match interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 209: Usb - Universal Serial Bus Interface

    To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 210: Operation

    EPT 1 time 18.3 Operation This section gives an overview of the USB module operation during normal transactions. For general details on USB and the USB protocol, please refer to http://www.usb.org and the USB specification documents. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 211 When an OUT token is detected, the USB module fetches the endpoint CTRL and STATUS register data from the addressed output endpoint in its endpoint configuration table. If the endpoint is disabled, the USB module returns to idle and waits for the next token packet. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 212 Finally, the transaction complete flag (TRNCOMPL0) and BUSNACK0 are set and TOGGLE is toggled if the endpoint is not isochronous. The transaction complete interrupt flag (TRNIF) in INTFLAGSBCLR/SET is set. The endpoint's configuration table address is written to the FIFO if the transaction complete FIFO mode is enabled. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 213 USB module returns to idle and waits for the next token packet. Figure 18-5. IN transaction. ADDRESS LEGAL READ EP STATUS IDLE ADDRESS ENDPOINT TOKEN MATCH? ENDPOINT? CONFIG ENABLED? READ STALL & STALL CONFIG NO ISO? BUSNACK0 ISO? SET? READ PAYLOAD UPDATE DATA ISO? DATA SET? STATUS XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 214: Sram Memory Mapping

    The USB module clock selection is independent of and separate from the main system clock selection. Selection and setup are done using the main clock control settings. For details, refer to “System Clock and Clock Options” on page Figure 18-7 on page 215 shows an overview of the USB module clock selection. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 215: Ping-Pong Operation

    Figure 18-8. Ping-pong operation overview. Endpoint single bank Without Ping-Pong Endpoint Double bank With Ping-Pong Bank0 Bank1 USB data packet Available time for data processing by CPU to avoid NACK XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 216: Multipacket Transfers

    If a short or oversized packet is received, the endpoint’s CNT register will be incremented by the data payload after the transaction has completed. TOGGLE will be toggled if the endpoint is not isochronous, and BUSNACK0/BUSNACK1, TRNIF, and TRNCOMPL0/TRNCOMPL1 will be set. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 217: Auto Zero Length Packet

    Reading the write pointer has no effect. The endpoint configuration table address can then be read directly from (EPPTR + 2 × FIFORP). Figure 18-11.USB transaction complete FIFO example. Ep X Ep Z FIFO FIFO FIFO FIFO FIFOWP FIFORP FIFORP FIFORP FIFORP FIFORP FIFOWP FIFOWP FIFOWP FIFOWP XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 218: Interrupts And Events

    18.10.1 Transaction Complete Interrupt The transaction complete interrupt is generated per endpoint. When an interrupt occurs, the associated endpoint number is registered and optionally added to the FIFO. The following two interrupt sources use the interrupt vector: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 219: Vbus Detection

    CRC error CRCIF Underflow/overflow UNFIF and OVFIF 18.11 VBUS Detection Atmel AVR XMEGA devices can use any general purpose I/O pin to implement a VBUS detection function, and do not use a dedicated VBUS detect pin. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 220: On-Chip Debug

    USB transactions. If there is an ongoing USB transaction, the USB module will acknowledge any OCD break request only when the ongoing USB transaction has been completed. The USB module will NACK any further transactions received from the USB host, whether they are SETUP, IN (ISO, BULK), or OUT (ISO, BULK). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 221: Register Description - Usb

    Setting this bit enables the pull-up on the USB lines to also be held when the device enters reset. The bit will be cleared on a power-on reset.  Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 222 This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.  Bit 6:0 – ADDR[6:0]: Device Address These bits contain the USB address the device will respond to. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 223 Unused bits will always be read as zero. +0x06 EPPTR[7:0] Read/Write Initial Value  Bit 7:0 – EPPTR[7:0]: Endpoint Configuration Table Pointer low byte This register contains the eight lsbs of the endpoint configuration table pointer (EPPTR). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 224 Bit 4 – STALLIE: STALL Interrupt Enable Setting this bit enables the STALL interrupt for the conditions that set the stall interrupt flag (STALLIF) in the INTFLAGSACLR/SET register. The INTLVL bits must be nonzero for the interrupts to be generated. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 225 CPU from sleep modes where the system clock is stopped, such as power-down and power-save sleep modes.  Bit 4 – RSTIF: Reset Interrupt Flag This flag is set when a reset condition has been detected on the bus. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 226 CAL registers from software. ++0x3A CAL[7:0] Read/Write Initial Value  Bit 7:0 – CAL[7:0]: PAD Calibration low byte This byte holds the eight lsbs of CAL. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 227 18.13.14CALH – Calibration register High +0x3B CAL[15:8] Read/Write Initial Value  Bit 7:0 – CAL[15:8]: PAD Calibration high byte This byte holds the eight msbs of CAL. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 228: Register Description - Usb Endpoint

    When this flag is set, the USB module will discard incoming data to data buffer 1 in an OUT transaction, and will not return any data from data buffer 1 in an IN transaction. For control, bulk, and interrupt endpoints, a NAK handshake is returned. This flag is cleared by writing a one to its bit location. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 229 The FIFO does not store this endpoint configuration table address upon transaction complete for the endpoint when interrupts are disabled for an endpoint. Clearing this bit enables all previously enables interrupts again. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 230 OUT or SETUP transaction for an OUT endpoint, or the number of bytes to be sent in the next IN transaction for an IN endpoint. +0x02 CNT[7:0] Read/Write Initial Value  Bit 7:0 – CNT[7:0]: Endpoint Byte Counter This byte contains the eight lsbs of the USB endpoint counter (CNT). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 231 This byte contains the eight lsbs of the endpoint data pointer (DATAPTR). 18.14.6 DATAPTRH – Data Pointer High register +0x05 DATAPTR[15:8] Read/Write Initial Value  Bit 15:0 - DPTR[15:8]: Endpoint Data Pointer High This byte contains the eight msbs of the endpoint data pointer (DATAPTR). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 232  Bit 7:0 – AUXDATA[15:8]: Auxiliary Data High This byte contains the eight msbs of the auxiliary data (AUXDATA). When multipacket transfer is not used, this SRAM location is free to use for other application data. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 233: Register Description - Frame

    These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.  Bit 2:0 – FRAMENUM[10:8]: Frame Number This byte contains the three msbs of the frame number (FRAMENUM). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 234: Register Summary - Usb Module

    +0x01 FRAMENUM FRAMEER – – – – FRAMENUM[10:8] 18.19 USB Interrupt Vector Summary Offset Source Interrupt Description 0x00 BUSEVENT_vect SOF, suspend, resume, bus reset, CRC, underflow, overflow, and stall error interrupts 0x02 TRNCOMPL_vect Transaction complete interrupt XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 235: Twi - Two-Wire Interface

    It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V voltage than used by the TWI bus. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 236: General Twi Bus Concepts

    (DATA) are transferred, the master issues a STOP condition (P) on the bus to end the transaction. The receiver must acknowledge (A) or not-acknowledge (A) each byte received. Figure 19-2 on page 237 shows a TWI transaction. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 237 19-4, a bit transferred on the SDA line must be stable for the entire high period of the SCL line. Consequently the SDA value can only be changed during the low period of the clock. This is ensured in hardware by the TWI module. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 238 NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP condition (P) directly after the address packet. There are no limitations to the number of data packets that can be XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 239 A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the slave to run at a lower system clock frequency. However, the overall performance of the bus will be reduced accordingly. Both XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 240 SCL line at the same time. The algorithm is based on the same principles used for the clock stretching previously described. Figure 19-10 shows an example where two masters are competing for control over the bus clock. The SCL line is the wired-AND result of the two masters clock outputs. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 241: Twi Bus State Logic

    The bus state can be unknown, idle, busy, or owner, and is determined according to the state diagram shown in Figure 19-11. The values of the bus state bits according to state are shown in binary in the figure. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 242: Twi Master Operation

    When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and will in most cases require software interaction. Figure 19-12 shows the TWI master operation. The diamond shaped symbols (SW) indicate where software interaction is required. Clearing the interrupt flags releases the SCL line. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 243 If the master receives an ACK from the slave, the master write interrupt flag is set and the master received acknowledge flag is cleared. The clock hold is active at this point, preventing further activity on the bus. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 244: Twi Slave Operation

    The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick command can be enabled to auto-trigger operations and reduce software complexity. Promiscuous mode can be enabled to allow the slave to respond to all received addresses. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 245: Enabling External Driver Interface

    When this mode is enabled, an external TWI compliant tri-state driver is needed for connecting to a TWI bus. By default, port pins 0 (Pn0) and 1 (Pn1) are used for SDA and SCL. The external driver interface uses port pins 0 to 3 for the SDA_IN, SCL_IN, SDA_OUT, and SCL_OUT signals. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 246: Register Description - Twi

    Table 19-2. External driver interface enable. EDIEN Mode Comment Normal TWI Two-pin interface, slew rate control, and input filter. Four-pin interface, standard I/O, no slew rate control, and no input External driver interface filter. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 247: Register Description - Twi Master

    Setting the inactive bus timeout (TIMEOUT) bits to a nonzero value will enable the inactive bus timeout supervisor. If the bus is inactive for longer than the TIMEOUT setting, the bus state logic will enter the idle state. Table 19-3 lists the timeout settings. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 248 START or STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 249 This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set when RIF or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag. The flag is also cleared automatically for the same conditions as RIF. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 250 The BAUD register must be set to a value that results in a TWI bus clock frequency (f ) equal or less than 100kHz or 400kHz, depending on which standard the application should comply with. The following equation [2] expresses equation [1] solved for the BAUD value: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 251 DATA register will trigger the bus operation as set by the ACKACT bit. If a bus error occurs during reception, WIF and BUSERR are set instead of RIF. Accessing the DATA register will clear the master interrupt flags and CLKHOLD. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 252: Register Description - Twi Slave

    CMD bits. If the SMEN bit in the CTRLA register is set, the acknowledge action is performed when the DATA register is read. Table 19-7 lists the acknowledge actions. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 253 Writing the CMD bits will automatically clear the slave interrupt flags and CLKHOLD, and release the SCL line. The ACKACT bit and CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 254 This flag indicates whether a valid address or a STOP condition caused the last setting of APIF in the STATUS register. Table 19-9. TWI slave address or stop. Description A STOP condition generated the interrupt on APIF Address detection generated the interrupt on APIF XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 255 If smart mode is enabled, reading the DATA register will trigger the bus operation as set by the ACKACT bit. Accessing the DATA register will clear the slave interrupt flags and CLKHOLD. When an address match occurs, the received address will be stored in the DATA register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 256 By default, this bit is zero, and the ADDRMASK bits acts as an address mask to the ADDR register. If this bit is set to one, the slave address match logic responds to the two unique addresses in ADDR and ADDRMASK. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 257: Register Summary - Twi

    STATUS APIF CLKHOLD RXACK COLL BUSERR +0x03 ADDR ADDR[7:0] +0x04 DATA DATA[7:0] +0x05 ADDRMAS ADDRMASK[7:1] ADDREN 19.14 Interrupt Vector Summary Offset Source Interrupt Description 0x00 SLAVE_vect TWI slave interrupt vector 0x02 MASTER_vect TWI master interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 258: Spi - Serial Peripheral Interface

    When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 20-1. The pins with user-defined direction must be configured from software to have the correct direction according to the application. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 259: Master Mode

    20-2. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 260: Dma Support

    DATA register. It is possible, however, to use the XMEGA USART in SPI mode and then have DMA support in master mode. For details, refer to “USART in Master SPI Mode” on page 276. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 261: Register Description

    These two bits control the SPI clock rate configured in master mode. These bits have no effect in slave mode. The relationship between SCK and the peripheral clock frequency ( clk ) is shown in Table 20-3. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 262 STATUS register when WRCOL is set, and then accessing the DATA register.  Bit 5:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 263: Register Summary

    MODE[1:0] PRESCALER[1:0] +0x01 INTCTRL – – – – – – INTLVL[1:0] +0x02 STATUS WRCOL – – – – – – +0x03 DATA DATA[7:0] 20.9 Interrupt vector Summary Offset Source Interrupt Description 0x00 SPI_vect SPI interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 264: Usart

    A block diagram of the USART is shown in Figure 21-1 on page 265. The main functional blocks are the clock generator, the transmitter, and the receiver, which are indicated in dashed boxes. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 265: Clock Generation

    The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are supported: normal and double-speed asynchronous mode, master and slave synchronous mode, and master SPI mode. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 266   BAUD BSCALE BSCALE ------------ -  BSE L  8((2 BAUD BAUD Synchronous and master SPI mode  BSEL -------------------- - 1 – ----------------------------------- - ------------ -    BAUD BAUD BSEL BAUD XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 267 XCK pin will be overridden. The dependency between the clock edges and data sampling or data change is the same. Data input (on RxD) is sampled at the XCK clock edge which is opposite the edge where data output (TxD) is changed. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 268 Rising, setup Falling, sample Falling, sample Rising, setup Falling, setup Rising, sample The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 269: Frame Formats

    (making the total number of ones even). If odd parity is selected, the parity bit is set to one if the number of logical one data bits is even (making the total number of ones odd). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 270: Usart Initialization

    Data Reception - The USART Receiver When the receiver is enabled, the RxD pin functions as the receiver's serial input. The direction of the pin must be set as input, which is the default pin setting. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 271: Asynchronous Data Reception

    Note the larger time variation when using the double speed mode of operation. Samples denoted as zero are samples done when the RxD line is idle; i.e., when there is no communication activity. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 272 Next Start Bit Sampling. For double speed mode, the first low level must be delayed to point (B). Point (C) marks a stop bit of full length at nominal baud rate. The early start bit detection influences the operational range of the receiver. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 273 Table 21-4. Recommended maximum receiver baud rate error for double speed mode. Recommended Max #(Data + Parity Bit) Max Total Error [%] Receiver Error [%] slow fast 94.12 105.66 +5.66/-5.88 ± 2.5 94.92 104.92 +4.92/-5.08 ± 2.0 95.52 104.35 +4.35/-4.48 ± 1.5 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 274: Fractional Baud Rate Generation

    BSEL and BSCALE settings when using the internal oscillators to generate the most commonly used baud rates for asynchronous operation and how reducing the BSCALE can be used to reduce the baud rate error even further. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 275 Error [%] 2400 4800 9600 14.4k -0.1 -0.1 19.2k -0.8 -0.8 28.8k -0.1 -0.1 38.4k -0.8 -0.8 57.6k -0.1 -0.1 76.8k -0.8 -0.8 115.2k -0.1 -0.1 -0.8 -0.8 230.4k -0.1 -0.1 -0.8 -0.8 460.8k -0.1 -0.1 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 276: Usart In Master Spi Mode

    UDORD bit functionality is identical to that of the SPI DORD bit  When the USART is set in master SPI mode, configuration and use are in some cases different from those of the standalone SPI module. In addition, the following differences exist: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 277: Multiprocessor Communication Mode

    Using any of the 5-bit to 8-bit character frame formats is impractical, as the receiver must change between using n and n+1 character frame formats. This makes full-duplex operation difficult, since the transmitter and receiver must use the same character size setting. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 278: Ircom Mode Of Operation

    “IRCOM - IR Communication Module” on page 285 21.14 DMA Support DMA support is available on UART, USRT, and master SPI mode peripherals. For details on different USART DMA transfer triggers, refer to “Transfer Triggers” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 279: Register Description

    DREIF is cleared by writing DATA. When interrupt-driven data transmission is used, the data register empty interrupt routine must either write new data to DATA in order to clear DREIF or disable the data register empty interrupt. If not, a new interrupt will occur directly after the return from the current interrupt. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 280 These bits enable the data register empty interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118. The enabled interrupt will be triggered when the DREIF flag in the STATUS register is set. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 281 – – – UDORD UCPHA – +0x05 Read/Write Initial Value Note: Master SPI mode.  Bits 7:6 – CMODE[1:0]: Communication Mode These bits select the mode of operation of the USART as shown in Table 21-7. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 282 Stop Bit(s)  Bit 2:0 – CHSIZE[2:0]: Character Size The CHSIZE[2:0] bits set the number of data bits in a frame according to Table 21-10 on page 283. The receiver and transmitter use the same setting. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 283 These are the upper 4 bits of the 12-bit value used for USART baud rate setting. BAUDCTRLA contains the eight least- significant bits. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing BAUDCTRLA will trigger an immediate update of the baud rate prescaler. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 284: Register Summary

    BAUDCTRL BSEL[7:0] +0x07 BAUDCTRL BSCALE[3:0] BSEL[11:8] 21.17 Interrupt Vector Summary Offset Source Interrupt Description 0x00 RXC_vect USART receive complete interrupt vector 0x02 DRE_vect USART data register empty interrupt vector 0x04 TXC_vect USART transmit complete interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 285: Ircom - Ir Communication Module

    IRCOM receiver. This will disable the RX input from the USART pin. For transmission, three pulse modulation schemes are available: 3/16 of the baud rate period  Fixed programmable pulse time based on the peripheral clock frequency  Pulse modulation disabled  XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 286 RX pin. If event system input is enabled, input from the USART's RX pin is automatically disabled. The event system has a digital input filter (DIF) on the event channels that can be used for filtering. Refer to “Event System” on page 65” for details on using the event system. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 287: Registers Description

    Bit 3:0 – EVSEL [3:0]: Event Channel Selection These bits select the event channel source for the IRCOM receiver according to Table 22-1. If event input is selected for the IRCOM receiver, the input from the USART’s RX pin is automatically disabled. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 288: Register Summary

    Event system channel n; n = {0, …,7} 22.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL – – – – EVSEL[3:0] +0x01 TXPLCTRL TXPLCTRL[7:0] +0x02 RXPLCTRL RXPLCTRL[7:0] XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 289: Aes And Des Crypto Engines

    (plaintext or ciphertext) is placed in registers R0-R7, where the LSB of data is placed in R0 and the MSB of data is placed in R7. The full 64-bit key (including parity bits) is placed in registers R8-R15, with the LSB of the key in R8 and the MSB of the key in R15. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 290: Aes Crypto Module

    Start the encryption/decryption operation. If more than one block is to be encrypted or decrypted, repeat the procedure from step 3. When the encryption/decryption procedure is complete, the AES interrupt flag is set and an optional interrupt is generated. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 291 CTRL Reset pointer reset or access to CTRL In the AES crypto module, the following definition of the key is used: In encryption mode, the key is the one defined in the AES standard.  XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 292 Same key as loaded loaded key last loaded subkey 23.4.2 DMA Support The AES module can trigger a DMA transfer when the encryption/decryption procedure is complete. For more details on DMA transfer triggers, refer to “Transfer Triggers” on page XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 293: Register Description - Aes

    –  Bit 1:0 Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 294 KEY register. After encryption/decryption is done, the last subkey can be read sequentially, byte-by-byte, through the KEY register. Loading the initial data to the KEY register should be done after setting the appropriate AES mode and direction. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 295 These bits enable the AES interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118. The enabled interrupt will be triggered when the SRIF in the STATUS register is set. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 296: Register Summary - Aes

    – – – +0x07 Reserved – – – – – – – – 23.7 Interrupt vector summary Table 23-2. AES interrupt vector and its offset word address. Offset Source Interrupt Description 0x00 AES_vect AES interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 297: Crc - Cyclic Redundancy Check Generator

    The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3).  CRC-16: Polynomial: Hex value: 0x1021  CRC-32: Polynomial: +x+1 Hex value: 0x04C11DB7 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 298: Operation

    CRC module will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can be XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 299: Crc Using The I/O Interface

    DATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. New data can be written for each cycle. The CRC complete is signaled by writing the BUSY bit in the STATUS register. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 300: Register Description

    0011 – Reserved for future use 0100 DMACH0 DMA controller channel 0 0101 DMACH1 DMA controller channel 1 0110 DMACH2 DMA controller channel 2 0111 DMACH3 DMA controller channel 3 1xxx – Reserved for future use XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 301 CHECKSUM. If CRC-16 is selected or the BUSY flag is set (i.e., CRC generation is ongoing), CHECKSUM will contain the actual content. +0x04 CHECKSUM[7:0] Read/Write Initial Value  Bit 7:0 – CHECKSUM[7:0]: Checksum byte 0 These bits hold byte 0 of the generated CRC. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 302: Register Summary

    SOURCE[3:0] +0x01 STATUS – – – – – – ZERO BUSY +0x02 Reserved – – – – – – – – +0x03 DATAIN DATAIN[7:0] +0x04 CHECKSU CHECKSUM[7:0] +0x05 CHECKSU CHECKSUM[15:8] +0x06 CHECKSU CHECKSUM[23:16] +0x07 CHECKSU CHECKSUM[31:24] XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 303: Lcd - Liquid Crystal Display

    To reduce hardware design complexity, the LCD includes integrated LCD buffers, an integrated power supply voltage and an innovative SWAP mode. Using SWAP mode, the hardware designers have more flexibility during board layout as they can rearrange the pin sequence on Segment and/or Common Terminal Buses. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 304 A start of new frame triggers an update of the Shadow Display Memory. The content of Display Memory is saved into the Shadow Display Memory. A Display Memory refresh is possible without affecting data that is sent to the panel. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 305: Block Diagram

    Figure 25-2. LCD Controller Block Diagram CTRLG CTRLB CTRLA CTRLH CTRLD CTRLC Timing Control & Swap Character Mapping DATA0 SEGx Shadow Analog DATA1 Display Switch Memory Array COMy DATAn Display Memory CTRLE LCD Power BIAS Supply CTRLF BIAS CAPH CAPL XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 306: Mode Of Operation

    1/3 bias is usually recommended for an LCD with three common terminals (1/3 duty). The waveform is shown in Figure 25-5 on page 307. SEG0-COM0 is the voltage across a segment that is “ON” and SEG0-COM1 is the voltage across a segment that is “OFF”. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 307 Default and the low power waveform is shown in Figure 25-7 on page 308 for 1/3 duty and 1/3 bias. For other selections of duty and bias, the effect is similar. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 308 LCD to avoid DC voltage across the segments, and a slowly fading image. This mode differs from the one enabled by SEGON = 0 (in CTRLA register) where the segment and common pins are always driven by the programmed waveform and where all the segments are “OFF”. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 309 . If XBIAS is cleared, V sources voltages from the Bandgap Reference. Otherwise, V must be powered externally. Note that when using external V , the fine contrast controlled by FCONT[5:0] bits of the CRTLG register is inoperative. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 310 1: These values are provided for design guidance only. They should be optimized for the application by the designer based on actual LCD specifications. 2: Bias generation can be provided by other sources of voltage than a division resistor. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 311 Segment terminals [39:32] = PG[0:7] , Port G (GPIO functions) Segment terminals [31:24] = PM[0:7] , Port M (GPIO functions) Segment terminals [23:20] = GND (pull down) Segment terminals [19:0] = SEG[19:0] , LCD (LCD functions) XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 312: Register Description - Lcd

    Bit 3 – SEGSWP: Segment Terminal Bus Swap Writing this bit to one inverts completely the order of the segment terminal bus (SEG[39:0]). The segment terminals un- selected by PMSK[5:0] are also affected (see Table 25-5 on page 313). XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 313 Table 25-6. LCD prescaler selection. Frame Rates ( CLKDIV[2:0] = 0, DUTY = Output From Ripple Counter PRESC F(clk ) = 32kHz F(clk ) = 32768Hz 500 Hz 512 Hz / 16 250 Hz 256 Hz XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 314 “Low Power Waveform” on page 307).  Bit 2 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 315 This extended interrupt mode generates a stable time base from the frame rate.  Bit 2 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 316 Bits 1:0 – BLINKRATE[1:0]: LCD Blink Rate The BLINKRATE bit-field defines the frequency of the hardware Display Blinking when the BLINKEN bit is set. Blink frequencies are shown in Table 25-10. Table 25-10. Blink frequencies. BLINKRATE[1:0] Blink frequency 0.5Hz XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 317 TDG[1:0] STSEG[5:0] Read/Write Initial Value  Bits 7:6 – TDG[1:0]: Type of Digit This bit-field specifies the number of segments and segment/common connections used to display a digit. See Table 25- Figure 25-11 on page 318. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 318 DCODE bit-field will be computed by the Digit Decoder, and converted to display codes, and then automatically written into the Display Memory according to the STSEG value. This Digit Decoder can be used when the LCD panel is defined with one or more of the configurations above in Figure 25-11 on page 318. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 319 Table 25-12 on page 320, Table 25-13 on page 321 Table 25-14 on page 322 show the DCODE[6:0] and display pattern. The table entry code, DCODE [6:0], is the 7-bit ASCII code of the digit. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 320 Table 25-12. 7-segments Character Table. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 321 Table 25-13. 14-segments Character Table. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 322 Table 25-14. 16-segments Character Table. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 323 Max_SEG is the maximal number of SEG terminals of the device,   means the integer part of xxx. Bit position of the segment (pixel) in the Data Memory register (between 0 and 7): bit_position = pixel_SEG % 8  Where: % is the modulo operation. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 324: Register Summary - Lcd

    FCINTLVL[1:0] +0x02 CTRLC – – PMSK[5:0] +0x01 CTRLB PRESC CLKDIV[2:0] LPWAV – DUTY[1:0] +0x00 CTRLA ENABLE XBIAS DATLCK COMSWP SEGSWP CLRDT SEGON BLANK 25.7 Interrupt Vector Summary Offset Source Interrupt Description 0x00 LCD_vect LCD Interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 325: Adc - Analog-To-Digital Converter

    Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The V /10 and the bandgap voltage can also be measured by the ADC. The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 326: Input Sources

    When differential input is enabled, all input pins can be selected as positive input, and input pins 0 to 3 can be selected as negative input. The ADC must be in signed mode when differential input is used. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 327 26.3.3 Single-ended Input For single-ended measurements, all input pins can be used as inputs. Single-ended measurements can be done in both signed and unsigned mode. The negative input is connected to internal ground in signed mode. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 328 Internal Gnd is the internal device gnd level. Internal Gnd is used as the negative input when other internal signals are measured in single-ended signed mode. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 329: Sampling Time Control

    /2V voltage  External voltage applied to AREF pin on PORTA  External voltage applied to AREF pin on PORTB  Figure 26-8. ADC voltage reference selection Internal 1.00V Internal VCC/1.6V VREF Internal VCC/2.0V AREFA AREFB XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 330: Conversion Result

    1111 1111 1111 1110 -2045 1000 0000 0011 1111 1000 0000 0011 -2046 1000 0000 0010 1111 1000 0000 0010 -2047 1000 0000 0001 1111 1000 0000 0001 -2048 1000 0000 0000 1111 1000 0000 0000 -VREF GAIN XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 331: Compare Function

    The ADC is clocked from the peripheral clock. The ADC can prescale the peripheral clock to provide an ADC Clock (clk ) that matches the application requirements and is within the operating range of the ADC. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 332 (indicated with the grey slope of the START trigger). The input source is sampled in the first half of the first cycle. Figure 26-13.ADC timing for one single conversion without gain. START ADC SAMPLE CONVERTING BIT XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 333 ADC clock cycle propagation delay. Figure 26-15.ADC timing for one single conversion with 2x gain. START ADC SAMPLE AMPLIFY CONVERTING BIT Figure 26-16.ADC timing for one single conversion with 8x gain. START ADC SAMPLE AMPLIFY CONVERTING BIT XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 334: Adc Input Model

    ADC sample time, T is one-half the ADC clock cycle given by:  --------------------- - 2 f  For details on R , and C , refer to the ADC electrical characteristic in the device datasheet. channel switch sample XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 335: Dma Transfer

    ADC is flushed and the next conversion is started. It is also important to clear pending events or start ADC conversion commands before doing a flush. If not, pending conversions will start immediately after the flush. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 336: Register Description - Adc

    Table 26-1. ADC current limitations. CURRLIMIT[1:0] Group Configuration Description No limit Low current limit, max. sampling rate 225kSPS Medium current limit, max. sampling rate 150kSPS HIGH High current limit, max. sampling rate 75kSPS XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 337 Table 26-3. ADC reference selection. REFSEL[2:0] Group Configuration Description INT1V 10/11 of bandgap (1.0V) INTVCC /1.6 AREFA External reference from AREF pin on PORT A AREFB External reference from AREF pin on PORT B INTVCC2 101 - 111 – Reserved XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 338 Table 26-5. ADC event mode select. EVACT[2:0] Group Configuration Event Input Operation Mode NONE No event inputs Event channel with the lowest number defined by EVSEL triggers conversion on ADC channel – Reserved – Reserved – Reserved XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 339 This flag is set when the ADC conversion is complete. If the ADC is configured for compare mode, the interrupt flag will be set if the compare condition is met. CH0IF is automatically cleared when the ADC interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 340 These are the eight lsbs of the 12-bit CAL value. 26.15.10CALH – Calibration Value register High +0x0D – – – – CAL[11:8] Read/Write Initial Value  Bit 3:0 – CAL[11:8]: Calibration value These are the four msbs of the 12-bit CAL value. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 341 These are the four lsbs of the 12-bit ADC result.  Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 342: Register Description - Adc Channel

    Bit 4:2 – GAIN[2:0]: Gain Factor These bits define the gain factor for the ADC gain stage. Table 26-7 on page 343. Gain is valid only with certain MUX settings. See “MUXCTRL – MUX Control registers” on page 343. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 343 – MUXPOS[3:0] MUXNEG[2:0] Read/Write Initial Value  Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 344 ADC14 pin 1111 PIN15 ADC15 pin Table 26-12. ADC MUXPOS configuration when INPUTMODE[1:0] = 11 (differential with gain) is used. MUXPOS[3:0] Group Configuration Description 0000 PIN0 ADC0 pin 0001 PIN1 ADC1 pin 0010 PIN2 ADC2 pin XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 345 Table 26-14. ADC MUXNEG configuration, INPUTMODE[1:0] = 11, differential with gain. MUXNEG[2:0] Group Configuration Analog Input PIN4 ADC4 pin PIN5 ADC5 pin PIN6 ADC6 pin PIN7 ADC7 pin INTGND Internal ground – Reserved – Reserved PAD ground XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 346 The interrupt flag is set when the ADC conversion is complete. If the channel is configured for compare mode, the flag will be set if the compare condition is met. IF is automatically cleared when the ADC channel interrupt vector is executed. The bit can also be cleared by writing a one to the bit location. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 347 These are the four lsbs of the 12-bit ADC result.  Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 348 This register gives the number of input sources included in the channel scan. The number of input sources included is COUNT + 1. The input channels included are the range from MUXPOS to MUXPOS + COUNT. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 349: Register Summary - Adc

    – +0x04 RESL RES[7:0] +0x05 RESH RES[15:8] +0x06 SCAN OFFSET COUNT +0x07 Reserved – – – – – – – – 26.19 Interrupt vector Summary Offset Source Interrupt Description 0x00 Analog-to-digital converter channel 0 interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 350: Ac - Analog Comparator

    The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 351: Input Sources

    (rising edge), or when the output changes from one to zero (falling edge). Events are generated at all times for the same condition as the interrupt, regardless of whether the interrupt is enabled or not. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 352: Window Mode

    Application software can select between no-, low-, and high hysteresis for the comparison. Applying a hysteresis will help prevent constant toggling of the output that can be caused by noise when the input signals are close to each other. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 353: Register Description

    27-2. For details on actual hysteresis levels, refer to the device datasheet. Table 27-2. Hysteresis settings. HYSMODE[1:0] Group Configuration Description No hysteresis SMALL Small hysteresis LARGE Large hysteresis – Reserved  Bit 0 – ENABLE: Enable Setting this bit enables analog comparator n. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 354 Table 27-4. Negative input MUX selection. MUXNEG[2:0] Group Configuration Negative Input MUX Selection PIN0 Pin 0 PIN1 Pin 1 PIN3 Pin 3 PIN5 Pin 5 PIN7 Pin 7 – Reserved BANDGAP Internal bandgap voltage SCALER voltage scaler XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 355 Bit 4 – WEN: Window Mode Enable Setting this bit enables the analog comparator window mode.  Bits 3:2 – WINTMODE[1:0]: Window Interrupt Mode Settings These bits configure the interrupt mode for the analog comparator window mode according to Table 27-5. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 356 Bit 1 – AC1IF: Analog Comparator 1 Interrupt Flag This is the interrupt flag for AC1. AC1IF is set according to the INTMODE setting in the corresponding “ACnCTRL – Analog Comparator n Control register” on page 353. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 357 The constant current source is calibrated during production. A calibration value can be read from the signature row and written to the CURRCALIB register from software. Refer to device data sheet for default calibration values and user calibration range. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 358: Register Summary

    +0x09 CURRCALIB – – – – CALIB[3:0] 27.10 Interrupt vector Summary Offset Source Interrupt Description 0x00 COMP0_vect Analog comparator 0 interrupt vector 0x02 COMP1_vect Analog comparator 1 interrupt vector 0x04 WINDOW_vect Analog comparator window interrupt vector XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 359: Ieee 1149.1 Jtag Boundary Scan Interface

    When the JTAGEN fuse is unprogrammed or the JTAG disable bit is set, the JTAG interface is disabled. The four TAP pins are normal port pins, and the TAP controller is in reset. When enabled, the input TAP signals are internally pulled high and JTAG is enabled for boundary scan operations. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 360 Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. If the selected data register has a latched parallel  output, the latching takes place in the update DR state. The exit DR, pause DR, and exit2 DR states are used only for navigating the state machine. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 361: Jtag Instructions

     connected to the pins 28.4.4 BYPASS; 0xf BYPASS is the instruction for selecting the bypass register for the data register. This instruction can be issued to make the shortest possible scan chain through the device. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 362: Boundary Scan Chain

    IN register value (tapped before the input inverter and input synchronizer). Mode represents either an active CLAMP or EXTEST instruction, while shift DR is set when the TAP controller is in its shift DR state. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 363: Data Registers

    Even though the PDI_DATA pin is bidirectional, it is only made observable in order to avoid any extra logic on the PDI_DATA output path. Figure 28-3. An observe-only input cell. To next cell From system To system logic 28.6 Data Registers The supported data registers that can be connected between TDI and TDO are: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 364 The part number is a 16-bit code identifying the device. Refer to the device data sheets to find the correct number. 28.6.2.3 Manufacturer ID The manufacturer ID is an 11-bit code identifying the manufacturer. For Atmel, this code is 0x01F. 28.6.3 Boundary Scan Chain The boundary scan chain has the capability of driving and observing the logic levels on all I/O pins.
  • Page 365 28.6.4 PDICOM Data Register The PDICOM data register is a 9-bit wide register used for serial-to-parallel and parallel-to-serial conversions of data between the JTAG TAP and the PDI. For details, refer to “Program and Debug Interface” on page 408. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 366: Program And Debug Interface

    Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level.
  • Page 367: Pdi Physical

    Figure 29-2. PDI connection. The remainder of this section is intended for use only by third parties developing programmers or programming support for Atmel AVR XMEGA devices. 29.3.1 Enabling The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width (refer to device datasheet for external reset pulse width data).
  • Page 368 The IDLE character is equal to a 12- bit length of high level. The BREAK and IDLE characters can be extended beyond the 12-bit length. Figure 29-5. Characters and timing for the PDI physical layer. 1 DATA character START STOP 1 BREAK character BREAK 1 IDLE character IDLE XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 369 1 DATA character Dir. change 1 DATA character IDLE bits Sp1 Sp2 PDI DATA Receive (RX) PDI DATA Transmit (TX) Data from Guard time Data from Programmer to # IDLE bits PDI interface PDI interface inserted to Programmer XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 370 As long as the PDI transmits alternating ones and zeros, collisions cannot be detected, because the PDI output driver will be active all the time, preventing polling of the PDI_DATA line. However, the two stop bits should always be transmitted as ones within a single frame, enabling collision detection at least once per frame. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 371: Pdi Controller

    The PDI has a small instruction set used for accessing both the PDI itself and the internal interfaces. All instructions are byte instructions. The instructions allow an external programmer to access the PDI controller, the NVM controller and the nonvolatile memories. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 372 Hence, the initial repeat counter value plus one gives the total number of times the instruction will be executed. Setting the repeat counter register to zero makes the following instruction run once without being repeated. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 373: Register Description - Pdi Instruction And Addressing Registers

    The instruction is retained until another instruction is loaded. The reason for this is that the REPEAT command may force the same instruction to be run repeatedly, requiring command decoding to be performed several times on the same instruction. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 374 Immediately after an instruction (except the LDCS and STCS instructions) a specified number of operands or data bytes (given by the size parts of the instruction) are expected. The operand count register is used to keep track of how many bytes have been transferred. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 375: Register Description - Pdi Control And Status Registers

    Table 29-1 on page 376. In order to speed up the communication, the guard time should be set to the lowest safe configuration accepted. No guard time is inserted when switching from TX to RX mode. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 376: Register Summary

    Bit 1 Bit 0 Page +0x00 STATUS – – – – – – NVMEN – +0x01 RESET RESET[7:0] +0x02 CTRL – – – – – GUARDTIME[2:0] +0x03 Reserved – – – – – – – – XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 377: Memory Programming

    30.2 Overview This section describes how to program the nonvolatile memory (NVM) in Atmel AVR XMEGA devices, and covers both self-programming and external programming. The NVM consists of the flash program memory, user signature and production signature rows, fuses and lock bits, and EEPROM data memory. For details on the actual memories, how they are organized, and the register description for the NVM controller used to access the memories, refer to “Memories”...
  • Page 378: Nvm Commands

    All NVM reads from the application section  During self-programming, interrupts must be disabled or the interrupt vector table must be moved to the boot loader sections, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 135. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 379: Flash And Eeprom

    Before programming a flash page with the data in the flash page buffer, the flash page must be erased. Programming an un-erased flash page will corrupt its content. The flash page buffer can be filled either before the erase flash Page operation or between a erase flash page and a write flash page operation: XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 380: Protection Of Nvm

    POR threshold (V ) level is enabled. During chip erase and when the PDI is enabled the brownout detector (BOD) POT+ is automatically enabled at its configured level. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 381: Crc Functionality

    382. The word address in the page (FWORD) is held by the bits [WORDMSB:1] in the Z- pointer. The remaining bits [PAGEMSB:WORDMSB+1] in the Z-pointer hold the flash page address (FPAGE). Together FWORD and FPAGE holds an absolute address to a word in the flash. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 382 15. CCP is not required for external programming. The two last columns show the address pointer used for addressing and the source/destination data register. Section 30.11.1.1 on page 381 through Section 30.11.2.14 on page 386 explain in detail the algorithm for each NVM operation. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 383 Load the Z-pointer with the byte address to read. Load the NVM command register (NVM CMD) with the no operation command. Execute the LPM instruction. The destination register will be loaded during the execution of the LPM instruction. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 384 30.11.2.7 Erase Application Section The erase application command is used to erase the complete application section. Load the Z-pointer to point anywhere in the application section. Load the NVM CMD register with the erase application section command XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 385 Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set, and the CPU is halted during the execution of the CRC command. The CRC checksum will be available in the NVM data registers. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 386 Table 30-3. Fuse and lock bit commands. Change Address Data CMD[6:0] Group Configuration Description Trigger Halted Protected Busy Pointer Register 0x00 NO_OPERATION No operation Fuses and Lock Bits 0x07 READ_FUSES Read fuses CMDEX ADDR DATA 0x08 WRITE_LOCK_BITS Write lock bits CMDEX ADDR XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 387 Together E2BYTE and E2PAGE hold an absolute address to a byte in the EEPROM. The size of E2WORD and E2PAGE will depend on the page and flash size in the device. Refer to the device datasheet for details on this. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 388 Address Data CMD[6:0] Group Configuration Description Trigger Halted Protected Busy Pointer Register 0x00 NO_OPERATION No operation EEPROM Page Buffer 0x33 LOAD_EEPROM_BUFFER Load EEPROM page buffer DATA0 ADDR DATA0 0x36 ERASE_EEPROM _BUFFER Erase EEPROM page buffer CMDEX XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 389 Load the NVM ADDR register with the address of the EEPROM page to write. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set until the operation is finished. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 390: External Programming

    PDI is enabled. Doing this all data and program memory spaces are mapped into the linear PDI memory space. Figure 30-3 on page 391 shows the PDI memory space and the base address for each memory space in the device. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 391 (i.e., to read from any NVM, the controller must be loaded with the NVM read command before loading data from the PDIBUS address space). For the reminder of this section, all references to reading and XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 392 CMDEX Boot Loader Section 0x68 Erase boot section PDI write 0x2A Erase boot loader section page PDI write 0x2C Write boot loader section page PDI write 0x2D Erase and write boot loader section page PDI write XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 393 Dedicated read EEPROM, read fuse, read signature row, and read production signature (calibration) row commands are also available for the various memory sections. The algorithm for these commands are the same as for the read NVM command. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 394 Load the NVM CMD register with Erase Application/ Boot/ EEPROM Section command Set the CMDEX bit in the NVM CTRLA register. The BUSY flag in the NVM STATUS register will be set until the operation is finished. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 395: Register Description

    30.14 Register Summary Refer to “Register Description – NVM Controller” on page 26 for a complete register summary of the NVM controller. Refer to “Register Summary” on page 421 for a complete register summary of the PDI. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 396: Peripheral Module Address Map

    Serial Peripheral Interface on port C page 263 0x08F0 IRCOM Infrared Communication Module page 288 0x0A00 TCE0 Timer/Counter 0 on port E page 175 0x0AA0 USARTE0 USART 0 on port E page 284 0x0D00 LCD - Liquid Crystal Display page 324 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 397: Instruction Set Summary

    Indirect Jump to (Z) PC(15:0) None  PC(21:16)  EIJMP Extended Indirect Jump to (Z) PC(15:0) None  PC(21:16) EIND  Jump None  RCALL Relative Call Subroutine PC + k + 1 None 2 / 3 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 398 (I = 0) then PC PC + k + 1 None 1 / 2 Data transfer instructions  Rd, Rr Copy Register None  MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None  Rd, K Load Immediate None XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 399 Rd, Z+ Extended Load Program Memory and Post- (RAMPZ:Z), None  Increment Z + 1  Store Program Memory (RAMPZ:Z) R1:R0 None  Store Program Memory and Post-Increment (RAMPZ:Z) R1:R0, None  by 2 Z + 2 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 400 Clear Carry  Set Negative Flag  Clear Negative Flag  Set Zero Flag  Clear Zero Flag  Global Interrupt Enable  Global Interrupt Disable  Set Signed Test Flag  Clear Signed Test Flag XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 401 (see specific descr. for WDR) None Notes: Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. One extra cycle must be added when accessing Internal SRAM. XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 402: Datasheet Revision History

    Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 33.1 8291B – 01/2013 Added XMEGA B feature overview inTable 2-1 on page References to Calibration Row updated to Production Signature Row for consistency. Added reference to “NVM Flash Commands”...
  • Page 403 “Bit 3:0 – COUNT[3:0]: Number of Input Channels Included in Scan” “SCAN – Input Channel Scan register” on page 348 Updated Analog Comparator overview block diagram in Figure 27-1 on page 351. 33.2 8291A – 07/2011 Initial revision edited from XMEGA AU Manual rev A 07/11 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 404: Table Of Contents

    Atmel AVR CPU ........
  • Page 405 Sleep Modes ..........97 XMEGA B [DATASHEET]...
  • Page 406 12.15 Register Summary – Ports ........149 XMEGA B [DATASHEET]...
  • Page 407 Features ........... . 201 XMEGA B [DATASHEET]...
  • Page 408 Interrupt vector Summary ........263 XMEGA B [DATASHEET]...
  • Page 409 Interrupt Vector Summary ........324 XMEGA B [DATASHEET]...
  • Page 410 Features ........... . 377 XMEGA B [DATASHEET]...
  • Page 411 Table of Contents ......... 404 XMEGA B [DATASHEET]...
  • Page 412 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 413 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 414 XMEGA B [DATASHEET] 8291B–AVR–01/2013...
  • Page 415 © 2012 Atmel Corporation. All rights reserved. / Rev.: 8291B–AVR–01/2013 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products.

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