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181
2.0 PIN DESCRIPTION
The Z-80 CPU
is
packaged
in an
industry standard 40 pin Dual In-Line Package. The
I/O
pins are shown in Figure
2.0-1 and the function of
each is described below.
/ M,
SYSTEM
J
CONTROL
1
MREQ
IORO
RD
WR
RFSH
'
HALT
WAIT
CPU
)
CONTROL
S
INT
'
NMI
RESET
CPU
BUS
CONTROL
{BUSRO
8USAK
-s
-
5V
GNO
27
30
19
31
32
20
33
21
34
22
35
28
36
37
18
38
39
24
40
1
16
2
3
17
Z-80
CPU
4
26
5
14
25
23
6
15
12
1 1
8
29
7
9
10
13
A0
N
A
I
A
?
A
J
A
4
A
1
A
i
A 7
A
ft
l
ADDRESS
(
BUS
A
-ÿ>
A
IC
An
A
l?
A
13
A
14
AiS
/
°0
D,
D,
Oj
O,
D5
D7
N
l.
DATA
?
BUS
/
Z-80 PIN CONFIGURATION
FIGURE 2.0-1
A0-Als
(
Address
Bus)
D0-D7
(Data
Bus)
Tri-state
output,
active
high.
A0-AiS
constitute
a
16-bit address bus.
The address bus
pro¬
vides the address for
memory (up
to
64K bytes) data exchanger and for
I/O
device data
exchanges.
I/O
addressing
uses
the 8
lower address bits
to
allow the
user
to
directly select
up
to
256
input or 256
output ports.
A0
is the least
significant address bit. During refresh
time,
the lower 7 bits contain a
valid refresh address.
Tri-state
input/output,
active high.
D0-D7
constitute an 8-bit
bidirectional data bus. The
data bus
is used
for
data exchanges with
memory'
and
I/O
devices.
M,
Output, active low. M,
indicates that
the
current
machine
cycle is
the OP code fetch cycle
(Machine Cycle one)
of
an
instruction
execution.
Note that during execution of 2-byte opcodes.
M, is generated
as
each op code byte is
fetched. These
two
byte opcodes
always
begin with CBH.
DDH,
EDH
or FDH. M, also occurs with
IORQ
to
indicate
an
interrupt acknowledge cycle.
MREQ
Tri-state
output,
active low. The memory
request
signal indicates that the address bus holds
(Memory
Request)
a
valid address for
a memory
read
or
memory write operation.
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