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163
As is shown in the figure,
a Z80 (Sharp
LH0080)
is used as the
CPU,
and is operated with a dock
of 2 MHz.
The
CPU
is reset when the
power is turned on or when the
reset
switch
is manually operated. The memory
configuration
corresponding to address buses
SOOOO-SFFFF
is
as follows.
SOOOO-SOFFF
is
used for the monitor program
(ROM);
the large 48
K
byte
space from S1000-SCFFF
is
used as
main memory (memory
from
S9000-SCFFF
is
optional);
addresses
from SDOOO on are used for
video RAM,
floppy
control,
and memory mapped
I/O.
The keyboard and cassette
tape
deck
are
controlled
by
means of
programmable peripheral interface
8255.
Further,
a rectangular audio
wave
generated by the output port
of
counter
1 of programmable interval timer
8253
is input
to
the
sound
generator,
which
outputs
sound
to
the speaker. The
two counters
other than this IC
serve as
internal clocks for
the
MZ-80A.
Table
3.1 shows the configuration of MZ-80A memory mapped
I/O.
Table
3.1
Assignment
of memory
mapped
I/O.
Address
Memory Read
Memory Write
Device
SEOOO
D7
: Resets cursor
timer
D3
~
D0
;
Key strobe
8255
SE001
D7
~
D0
;
Key
data
SE002
D7
: V-Blank
D6
: Status of cursor
timer
Ds
:
Read
data (cassette)
D4
:
READ/WRITE
status (cassette)
D3
: Motor
ON/OFF
(cassette)
D2
:
Masking
of
timer interrupt
D,
;
Write data (cassette)
D0
: V-Gate
SE003
Mode control
SE004
Setting
of
counter
#0
8253
SE005
Reading of counter
#
1
Setting
of
counter
#
1
SE006
Reading
of
counter
# 2
Setting
of counter
#2
SE007
Mode
control
SE008
D7
: Status of
tempo timer
D„
:
H-Blank
D0
;
Sound
ON/OFF
SEOOC
Memory
swap
SE010
Resets memory swap
SE014
Normal (CRT display)
SE015
Reverse
(CRT display)
SE200
SE2FF
Roll up/roll down
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