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206
Figure
4.0-1
is
a summary of
the
effect of different
instructions
on
the
two
enable flip flops.
Action
IFF
i
IFF;
CPU Reset
0
0
DI
0
0
El
1
1
LD
A,
I
•
•
IFF;
-*
Parity flag
LDA.R
•
•
IFFj
Parity
Hag
Accept
NMI
0
•
RETN
IFF2
•
IFF2
-
IFF,
indicates no change
FIGURE 4.0-1
INTERRUPT ENABLE/DISABLE FLIP FLOPS
CPU RESPONSE
Non Maskable
A nonmaskable interrupt will be accepted at all times by the
CPU.
When this
occurs,
the
CPU
ignores the next
instruction that it
fetches and instead does a
restart
to
location 0066H.
Thus,
it
behaves exactly as
if
it
had received a
restart instruction
but.
it is to
a location that
is not
one of
the 8 software
restart
locations. A
restart is merely
a call
to
a
specific address in
page 0 of memory.
Maskable
The CPU can be programmed
to
respond
to
the maskable interrupt
in
any one of three possible modes.
Mode 0
This mode
is
identical
to the
8080A
interrupt
response mode.
With this mode, the interrupting device
can
place
any
instruction
on
the data bus and the
CPU
will execute
it. Thus,
the interrupting device provides the
next
instruction
to
be executed instead
of
the
memory. Often this
will be a restart instruction since the interrupting device only need
supply a single byte instruction. Alternatively,
any other
instruction
such as a 3 byte call
to
any location
in
memory
could be executed.
The number of clock cycles
necessary
to execute
this instruction is 2
more
than the normal number for the instruc¬
tion.
This occurs
since
the
CPU
automatically adds
2
wait states
to
an
interrupt
response cycle
to
allow sufficient
time
to
implement
an
external daisy chain for priority control.
After
the
application of RESET the CPU will
automatically enter
interrupt
Mode
0.
Mode 1
When this mode has been selected by the programmer, the
CPU
will respond
to
an interrupt by
executing
a restart
to
location 003SH. Thus the response
is
identical
to
that for
a
non maskable
interrupt except that the call location
is
0038H
instead of
0066H.
Another difference
is
that the number of cycles required
to
complete the restart instruction
is
2 more than normal due
to
the
two
added
wait
states.
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