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TMS32020
DIGITAL
SIGNAL
PROCESSOR
•
200-ns
Instruction
Cycle
Time
•
544
Words
of
Programmable On-Chip Data
RAM
•
128K Words
of
Data/Program
Space
•
Sixteen
Input
and
Sixteen
Output Channels
•
16-Bit
Parallel
Interface
•
Directly
Accessible External
Data
Memory
Space
•
Global
Data
Memory
Interface
•
1
6-Bit
Instruction
and Data
Words
•
32-Bit
ALU
and Accumulator
•
Single-Cycle
Muitipiy/Accumulate
Instructions
•
0
to 16-Bit
Scaling
Shifter
•
Bit
Manipulation
and
Logical Instructions
•
Instruction
Set Support
for
Floating-Point
Operations
•
Block
Moves
for
Data/Program
Management
PIN
ASSIGNMENTS
PIN
FUNCTION
1
PIN
FUNCTION
1
PIN
FUNCTION
A2
08
C11
CLK0UT1
J10
55
A3
010
01
04
J11
:
15
A4
012
02
03
K1
AO
AS
014
010
CLK0UT2
K2
A1
A6
v
cc
Oil
XF
K3
A3
A7
h5lo
El
02
K4
AS
A8
r5
E2
01
KS
A7
A9
cjcx
E
1
HOLDA
K6
A8
A10
Vcc
Ell
OX
K7
A10
81
Vss
FI
DO
K8
A12
82
07
.
F2
577
^
K9
A14
83
09
F10
FSX
K10
35
84
011
FI
1
X2/CLK1N
K11
Vss
BS
013
G1
InTo
L2
Vss
B6
015
G2
TfsTTi
L3
A2
B7
513
G10
XI
L4
A4
88
READY
G11
55
15
A6
89
CIXR
HI
InT2
L6
Vcc
810
v cc
H2
vcc
L7
A9
811
IA.CK
H10
5Yrb
13
All
Cl
06
HI
1
R/VV
19
A13
C2
OS
J1
OR
110
A
1
CIO
J2
FSR
MARCH
1985—
REVISED
MAY
1986
•
Repeat
Instructions
for Efficient
Use
of
Program Space
•
Five Auxiliary
Registers
and Dedicated
Arithmetic Unit
for Indirect
Addressing
•
Serial
Port
for
Direct
Codec
Interface
•
Synchronization Input
for
Synchronous
Multiprocessor Configurations
•
Wait
States
for
Communication
to
Slow
Off-Chip Memories/Peripherals
•
On-Chip Timer
for
Control
Operations
•
Three
External
Maskable
User
Interrupts
•
Input Pin Polled
by
Software Branch
Instruction
•
Programmable Output
Pin
for
Signalling
External
Devices
•
2.4-Micron
NMOS
Technology
•
Single
5-V Supply
•
On-Chip Clock Generator
68
-PIN
GS
PIN
GRID
ARRAY
CERAMIC
PACKAGE
T
(TOP VIEW!
1
23456789
10
11
*
See
Pm
Assignments
Taoie (Page
II
and
Pin
Nomenclature
Taoie
(Page
2) (or
location
and
description
of
all
pms.
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