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IC BLOCK DIAGRAM & DESCRIPTION
IC820 ZR36732 (MPEG)
Pin
Name
Type
17
HD [7]
3-S
18
HD [6]
3-S
20
HD [5]
3-S
21
HD [4]
3-S
22
HD [3]
3-S
23
HD [2]
3-S
24
HD [1]
3-S
25
HD [0]
3-S
For 16 bits mode, the 8 l.s. data lines of host data bus. For 8 bits mode, only these signals are defined as host data
signals.
9
HD [11]
3-S
11
HD [10]
13
HD [9]
15
HD [8]
When HWID is connected to VDDP, these are data lines 11:8 of the 16-bit host data bus.
5
HD [15]
3-S
6
HD [14]
HD [13]
7
HD [12]
8
When HWID is connected to VDDP, these are data lines 15:12 of the 16-bit host data bus. When HWID is connected to
2
GNDP, these are the CD-DSP I
S input port pins, as explained in the CD-DSP pin description.
HA [3]
27
I
28
HA [2]
I
29
HA [1]
I
30
HA [0]
I
Host address inputs. These input signals indicate the register accessed in every cycle on the host interface.
32
HCS#
I
Host chip-select input.
ó
31
HWR#
HR/W#
I
In host protocol Type A ( HTYPE = GNDP): HR/W# . This input determines the direction of the host access.
In host protocol Type B ( HTYPE = VDDP): HWR# . Host write input.
ó
34
HRD#
HDS#
I
In host protocol Type A ( HTYPE = GNDP): HDS# . Data strobe input (active low).
In host protocol Type B ( HTYPE = VDDP): HRD# . Host read input (active low.)
36
HRDY
3-S
Host ready output. When this signal is tri-stated (i.e., it requires a pull-up resistor), up to SysConfig.CodBurstLen bytes of
code can be written to the Decoder with no need to poll its condition in between. When HRDY is low during a host
access, the Decoder may still receive at least two additional bytes of code without corrupting the data.
37
HIRQ#
3-S
Interrupt request. This output signal requests an interrupt from the host controller, if one of the events associated to
interrupts occurs, and it is not masked-off. It is de-asserted if the host responds to the interrupt by reading the interrupt
status register, or if the host disables the interrupt, or after RESET.
Deassertion of the HIRQ# output has two modes: De-activated and then tri-stated or directly to is a tri-state condition.
The pin needs external pull-up resistor.
39
HACK#
3-S
Host acknowledge output. In protocol A, the Decoder indicates that a read or write cycle is completed by asserting this
output. In protocol B, this signal is used by the Decoder to indicate a wait state that may be used by fast hosts. In protocol
B the host may ignore the HACK# signal.
When this signal is deasserted it is de-activated and then tri-stated. This pin needs an external pull-up resistor.
Pin
Name
Type
Video Syncs a nd Clocks Interface (5 pins).
127
VCLK
2
3-S
X
Main video clock. 27.000MHz.
VCLK
92
3-S
A division by two of the VCLK
2 signal. This signal is used as a sync qualifier.
X
95
HSYNC
3-S
Horizontal sync. Polarity and duration are programmable.
93
VSYNC
3-S
Vertical sync. Polarity and duration are programmable.
96
FI
3-S
Field indication. Polarity is programmable.
Analog Video Encoder Interface (7 pins).
102
CVBS/G/Y
O
(DAC A)
When the Decoder outputs composite video, this line is CVBS
When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV, this line is the Y output
105
Y/R/V
O
(DAC B)
When the Decoder outputs the composite video, this line is Y
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV, this line is the V output
106
C/B/U
O
(DAC C)
When the Decoder outputs the composite video, this line is C
When the Decoder outputs RGB, this line is the Blue output
When the Decoder outputs YUV, this line is the U output
103
CVBS/C
O
(DAC D)
When the Decoder outputs any of the types of video, this line can be programmed to output either composite or C.
RSET
108
I
Resistive load for gain adjustment of the DACs
111
VREF
I
Voltage reference for gain adjustment of the DACs
100
COSYNC
3-S
Composite sync output. Active only when RGB analog output is selected. Otherwise, the signal is low.
Pin
Name
Type
Reset, Standby and Idle Status Interface (3 pins)
124
RESET#
I
Reset input. Once de-asserted, the Decoder starts the initialization process.
122
STNDBY#
I
Stand-by input. When asserted together with RESET# , all outputs and bidirectional pins float, such that the Decoder is
electrically disconnected from its surroundings. All internal clocks are disabled, and the power consumption is minimized.
160
IDLE
3-S
Idle, Init and Reset states indication output.
Host Interface (29 pins)
2
HWID
I
Determines the width of the host interface data bus. It is allowed to be changed only during RESET. A low level (GNDP)
configures the Decoder to an 8-bit host data interface, a high level (VDDP) to 16-bit width.
1
HORD
I
Determines the order of bytes on the host interface data bus in case of 16-bit width ( HWID at VDDP). It is allowed to be
changed only during RESET. A low level (GNDP) configures the Decoder to input/output the m.s. byte on HD [15:8], a
high level (VDDP) to input/output the m.s. byte on HD [7:0]. Must be at GNDP if the host data bus is 8 bits.
4
HTYPE
I
Determines the protocol type for the 8 and 16 bits modes host interface. It is allowed to be changed only during RESET.
A low level (GNDP) configures the Decoder to type A, a high level (VDDP) to type B.
Status Afte r RESET/
Direct io n
During STANDBY
I/O (r.t.)
Reset: input (p.d.)
I/O (r.t.)
Standby: 3-S (p.d.)
I/O (r.t.)
I/O (r.t.)
I/O (p.u.)
I/O (r.t.)
I/O (r.t.)
I/O (p.u.)
I/O (p.d.)
Reset: input (p.d.)
I/O (r.t.)
Standby: 3-S (p.d.)
I/O (r.t.)
I/O (r.t.)
I/O (r.t.)
Reset: input (p.d.)
I/O (r.t.)
Standby: 3-S (p.d.)
I/O (r.t.)
I/O (r.t.)
I
Input
I
I
I
I
Input
I
Input
I
Input
O (p.d.)
Reset: output (low)
Standby: 3-S
O (p.u.)
3-S (p.u.)
O (p.u.)
Reset: output (high)
Standby: 3-S (p.u.)
Status Afte r RESET/
Direct io n
During STANDBY
O (r.t.)
Reset:
Standby: 3-S (p.d.)
O (r.t.)
Reset:
Standby: 3-S (p.d.)
O (r.t.)
Reset:
Standby: 3-S (p.d.)
O (r.t.)
Reset:
Standby: 3-S (p.d.)
O (r.t.)
Reset:
Standby: 3-S (p.d.)
AO
Reset:
Standby: 3-S
AO
Reset:
Standby: 3-S
AO
Reset:
Standby: 3-S
AO
Reset:
Standby: 3-S
AI
AI
O (p.d.)
Reset: output (low)
Standby: 3-S
Status Afte r RESET/
Direct io n
During STANDBY
I
Input
I
Input
O (p.u.)
Reset: output (high)
Standby: 3-S (p.u.)
I
Input
I
Input
I
Input
Pin
Name
General Purpos e I/O (Hos t Interface) (3 pi ns ).
134
GPAIO
General purpose input/output pin, monitored/controlled by the audio processor software. After RESET, this pin is defined
as input. Its definition can be configured through ADP commands.
145
GPSI
General purpose input, monitored by the system de-multiplexer/video processor software.
143
GPSO
General purpose output, controlled by the system de-multiplexer/video processor software. After RESET it outputs a low
level.
151
DVDREQ
DVD-DSP data request output (programmable polarity).
149
DVDVALID
DVD-DSP data valid input (programmable polarity).
148
DVDSOS
DVD-DSP start of sector input (programmable polarity).
159
DVDDAT [7]
158
DVDDAT [6]
157
DVDDAT [5]
156
DVDDAT [4]
155
DVDDAT [3]
154
DVDDAT [2]
153
DVDDAT [1]
152
DVDDAT [0]
DVD-DSP data input bus.
DVDSTRB
150
DVD-DSP data bit strobe (clock) input. Programmable polarity.
DVDERR
147
DVD-DSP error indication input. Programmable polarity.
CDERR
5
6
CDFRM
7
CDDAT
CDCLK
8
When HWID is connected to GNDP, these are the CD-DSP I
CDERR : data error indication input
CDFRM : left/right channel frame input
CDDAT : data input
CDCLK : bit clock input
When HWID is connected to VDDP, these are HD [15:12] of the host data bus, as explained in the host interface pin
description.
Pin
Name
131
AMCLK
Audio Master Clock input/output. 128, 192, 256, 384 or 512 times the sampling frequency (programmable).
133
S/PDIF ( AOUT [3])
S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately can be used as a fourth audio output.
After RESET this pin outputs low level.
138
AOUT [2]
137
AOUT [1]
136
AOUT [0]
Serial outputs of digital stereo audio.
113
AIN
Serial input of digital stereo audio.
139
AL RCLK
Digital audio left/right select output for the audio port. Square wave, at the sampling frequency. Programmable polarity
interpretation for input.
141
ABCL K
Digital audio bit-clock output. Data on AOUT and AIN is output or latched, respectively, with the rising or falling
(programmable) edge of this clock.
120
GCLK
27.000MHz clock or crystal input for main processing clock generation.
117
GCLK1
27.000MHz clock input for audio master clock generation. In normal operation must be connected to GCLK .
XO
119
Output to a crystal that is connected to GCLK . If a crystal is not used at GCLK , XO must be left not connected.
PLLC FG [1]
115
118
PLLC FG [0]
PLL configuration inputs. Allowed to be changed only during RESET. In normal operation both pins must be connected to
GNDP.
- 38 -
Status Afte r RESET/
Type
Direct io n
During STANDBY
3-S
I/O (r.t.)
Reset: input
Standby: 3-S
I
I
Input
O
O (p.d.)
Reset: output (low)
Standby: 3-S
DVD-DSP Interface (13 pins).
O
O (p.d.)
Reset: output (low)
Standby: 3-S
I
I
Input
I
I
Input
I
I
Input
I
I
Input
I
I
Input
CD-DSP Interface (4 pi ns ).
I
I/O (r.t.)
Reset: input (p.d.)
I
I/O (r.t.)
Standby: 3-S (p.d.)
I
I/O (r.t.)
I
I/O (r.t.)
2
S input port pins as follows:
Status Afte r RESET/
Type
Direct io n
During STANDBY
Digi tal Audi o Interface (8 pi ns ).
3-S
I/O (p.u.)
Reset: input
Standby: 3-S
O
O (p.d.)
Reset: input
Standby: 3-S
O
O (p.d.)
Reset: output (low)
Standby: 3-S
I
I
Input
O
O (p.d.)
Reset: output (low)
Standby: 3-S
O
O (p.d.)
Reset: output (low)
Standby: 3-S
PLL/Clock In terface (5 pins).
I
I
Input
I
I
Input
O
AO
I
I
Input
I
I
Input
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