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IC BLOCK DIAGRAM & DESCRIPTION
IC251 LC72722(RDS Signal Processer)
VREF
FLOUT CIN
1
5
Vdda
3
REFERENCE
VOLTAGE
4
Vssa
57kHz
BPF
SMOOTHING
ANTIALIASING
(SCF)
MPXIN
2
FILTER
FILTER
DO
20
R A M
CL
21
(24 BLOCK DATA)
C C B
DI
22
CE
23
T1
7
MEMORY CONTROL
T2
8
TEST
T3 to T7
9~11,16,17
Pin No.
Pin name
1
VREF
Reference voltage output (Vdda/2)
2
MPXIN
Baseband (multiplexed) signal input
5
FLOUT
Subcarrier oitput (filter output)
6
CIN
Subcarrier input (comparator input)
3
Vdda
Analog power supply (+5V)
4
Vssa
Analog ground
12
XOUT
Crystal oscillator output (4.332/8.664MHz)
13
XIN
Crystal oscillator input (external reference signal input)
7
T1
Test input (This pin must always be connected to ground.)
Test input (standby control)
8
T2
0:Normal operation.
1:Standby state (crystal oscillator stopped)
9
T3 (RDCL)
Test I/O (RDS clock output)
10
T4 (RDDA)
Test I/O (RDS data output)
11
T5 (RSFT)
Test I/O (soft decision control data output)
16
T6 (ERROR/57K/TP/BE1)
Test I/O (error status, regenceratcd carrier, TP, error block count outputs)
17
T7 (CORREC/ARI-ID/TA/BEO)
Test I/O (error corrcction status, SK datection,TA, error block count outputs)
18
SYNC
Block synchronization output
19
RDS-ID
RDS datection
20
DO
Data output
21
CL
Clock input
22
DI
Data input
23
CE
Chip enable
24
SYR
Synchronization and RAM address reset (active high)
14
Vddd
Digital power supply (+5V)
15
Vssd
Digital ground
* Normally the output pin. Used as an I/O pin in test mode, which is not available to user applications.
IC412 KA7805R(Voltage Regulator)
INPUT
1
CURRENT
GENERATOR
STARTING
REFERENCE
CIRCUIT
VOLTAGE
6
CLOCK
14
PLL
RECOVERY
(57kHz)
(1187.5Hz)
15
VREF
DATA
19
DECODER
18
ERROR CORRECTION
SYNC/EC CONTROLLER
(SOFT DECISION)
24
CLK(4.332MHz)
SYNC
SYNC
DETECT-1
DETECT-2
OSC / DIVIDER
13
12
XIN
XOUT
Function
Serial data interface (CCB)
SERIES
3
PASS
ELEMENT
SOA
PROTECTION
ERROR
AMPLIFIER
THERMAL
PROTECTION
2
IC410,411 PQ1CG21H2RZ(Chopper Regulator)
Vddd
V
1
IN
Constant-
Vssd
voltage
circuit
RDS-ID
SYNC
Q
Overcurrent
SYR
detection
circuit
S
Overheat
detection
circuit
I/O
O
I
IC450 CD4052BCM(Analog Mulutiplexer/
O
Demoltiplexer)
I
-
-
IN/OUT
O
V
2x
DD
16
15
I
I/O*
1
2
By
2y
IN/OUT
O
INPUT STATES
I
INHIBIT
C
0
0
0
0
-
0
0
-
0
0
1
0
0
1
0
1
1
0
1
-
OUTPUT
V
DD
16
BINARY
B
10
TO
LOGIC
1 DF 4
C
9
LEVEL
DECODER
CONVERSION
GND
WITH
INH
6
INHIBIT
8
7
V
V
SS
- 29 -
ON/OFF
Circuit
-
+
Soft start
R
OSC
-
+
3
COM
IN/OUT
OUT/IN
1x
x
0x
3x
A
B
9
14
13
12
11
10
8
3
4
5
6
7
y
3y
1y
INH
V
V
EE
SS
OUT/IN
IN/OUT
"ON" CHANNELS
B
A
CD4052B
0
0
0X, 0Y
1X, 1Y
0
1
1
0
2X, 2Y
1
1
3X, 3Y
0
0
0
1
1
0
1
1
-
-
NONE
X CHANNEL IN/OUT
3
2
1
0
11
15
14
12
TG
TG
TG
TG
TG
TG
TG
TG
1
5
2
4
B
1
2
3
EE
Y CHANNEL IN/OUT
2
V
OUT
5
ON/OFF
4
Oadj
COMMON X
13
OUT/IN
COMMON Y
3
OUT/IN
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