Advertisement
IC BLOCK DIAGRAM & DESCRIPTION
IC460,461,470,471,480,481,490,495 KIA4558F,
NJM4558M(Dual Low Noise Operational Amplifier)
1
OUT A
2
-IN A
+IN A
3
V
4
EE
IC462,472 LM1876 (Dual 20W audio Power Amplifier)
15
Vcc B
14
Standby B
13
+ In B
12
- In B
11
Mute B
10
GND B
9
Standby A
8
+ In A
7
- In A
6
Mute A
5
GND A
4
V
3
Out A
2
V
1
Out B
IC482 LM4700TF (30w audio Power Amplifier)
11
STANDBY
10
V
9
V
8
MUTE
7
GND
6
NC
5
NC
4
V
3
OUTPUT
2
NC
1
V
IC483 LM3876TF (56w audio Power Amplifier)
11
NC
10
V
9
V
8
MUTE
7
GND
6
NC
5
NC (+)
4
V-
3
OUTPUT
2
NC
1
V+
V
8
CC
A
7
OUT B
B
-IN B
6
5
+IN B
Vcc
A
2
+In A
8
Amp A
-In A
7
EE
4
5
A
CC
V
GND
EE
A
Vcc
+
IN
1
-
IN
V
+
10
IN
V
-
9
IN
EE
4
7
CC
V
GND
EE
V+
+
IN
1
-
IN
V
+
10
IN
V
-
9
IN
7
4
GND
V-
IC601 PT6315 (VFD Driver/Controller)
DIN
7
Serial
DOUT
6
Data
CLK
8
Interface
9
STB
OSC
5
OSC
LED1
1
LED
LED2
2
Driver
LED3
3
LED4
4
Pin Name
LED1 to LED4
OSC
DOUT
3
Out A
DIN
(Schmitt Trigger)
CLK
(Schmitt Trigger)
STB
(Schmitt Trigger)
K1 to K2
VSS
VDD
SG1/KS1 to SG16/KS16
VEE
SG17/GR12 to SG24/GR5
GR4 to GR1
3
OUTPUT
IC801 AT24C02N-10SI-2.7 (EEPROM)
VCC
8
GND
4
WP
7
START
SCL
6
STOP
SDA
5
LOGIC
DEVICE
ADDRESS
COMPARATOR
A
2
3
3
OUTPUT
A
2
1
A
1
0
D
IN
- 32 -
Control
Segment
Display Memory
(24 bits x 17 Words)
Key Scan
TI~inc Generator
Key Moter Memory
Driving Circuit
10
11
13
30
K1
K2
VDD
GND
VEE
I/O
Description
O
LED Output Pin
Oscillator Input Pin
I
A resistor is connected to this pin to
determinc the oscillation frequency
Data Output Pin (N-Channel, Open-Drain)
O
This pin outputs scrial data at the falling
cdge of the shift clock (starting from the lower bit)
Data Input Pin
I
This pin inputs serial data at the rising cdge
of the shift clock (starting from the lower bit)
Clock Input Pin
I
This pin reads serial data at the rising cdge
and outputs data at the falling cdge.
Serial Interface Strobe Pin
The data input after the STB has fallen is
I
processed as a command.
When this pin "HIGH",CLK is ignored,
Key Data Input Pins
I
The data inputted to these pins are fatched
at the end of the display cycle.
-
Logic Ground Pin
-
Logic Power Supply
High-Voltage Segment Output Pins
O
Also acts as the Key Source
-
Pull-Down Level
O
High Voltage Segment/Grid Output Pins
O
High-Voltage Grid Output Pins
SERIAL
FN
CONTROL
LOGIC
LOAD
COMP
LOAD
INC
R/W
DATA WORD
ADDR/COUNTER
V DEC
D
OUT
14
SG1/KS1
15
SG2/KS2
16
SG3/KS3
17
SG4/KS4
18
SG5/KS5
19
SG6/KS6
20
SG7/KS7
Driver
21
SG8/KS8
22
SG9/KS9
Grid
23
Driver
SG10/KS10
24
SG11/KS11
25
SG12/KS12
Output
26
SG13/KS13
27
SG14/KS14
28
SG15/KS15
30
SG16/KS16
31
SG17/GR12
32
SG18/GR11
33
SG19/GR10
34
SG20/GR9
35
SG21/GR8
36
SG22/GR7
37
SG23/GR6
38
SG24/GR5
42
GR1
41
GR2
Grid
Driver
GR3
40
39
GR4
Pin No.
1 to 4
5
6
7
8
9
10, 11
12, 44
13, 43
14 to 29
30
31 to 38
39 to 42
H.V. PUMP/TIMING
DATA RECOVERV
EEOROM
SERIAL MUX
D
/ACK
OUT
LOGIC
Advertisement
