Figure 5.1-2 - Single Stage Circuit Breaker Fail Timing; Figure 5.1-3 - Two Stage Circuit Breaker Fail Timing - Siemens 7SR210 Application Manual

50BF DTL1/50BF DTL2
The time delays run concurrently within the relay. The time delay applied to the CB Fail protection must be in
excess of the longest CB operate time + relay reset time + a safety margin.
First Stage (Retrip)
Trip Relay operate time
Reset Time
CB Tripping time
Safety Margin
Overall First Stage CBF Time Delay
Second Stage (Back Trip)
First CBF Time Delay
Trip Relay operate time
CB Tripping time
Reset Time of measuring element
Margin
Overall Second Stage CBF Time Delay
The safety margin is extended by 1 cycle for the second CBF stage as this will usually involve a back-trip of a
Busbar tripping scheme.
The timing sequence for each stage of the circuit breaker fail function is as below.
Relay
Operation
and CBF
Timer
Started
System
Fault
Main
does not occur
Trip
Failure of
Relay
CB to trip
Operation
20 40 60 80
CB Operate Time
Stage 1 CBF Timer (Backtrip) = 120ms

Figure 5.1-2 - Single Stage Circuit Breaker Fail Timing

Relay
Operation
and CBF
Timer
Started
System
Fault
Main
CBF elements
CB's
Trip
Fails to
Relay
Trip
Operation
40 60 80
CB Operate Time
Stage 1 CBF Timer (Retrip) = 120ms
©2011 Siemens Protection Devices Limited
260ms
Backtrip
Trip Relay
Reset of
CBF elements
Backtrip
Operation
100 120 140 160 180
CBF Retrip
Trip Relay
No Reset of
CBF Retrip
Operation
Failed CB Retrip
Operation
100 120 140 160 180
Stage 2 CBF Timer (Backtrip) = 250ms

Figure 5.1-3 - Two Stage Circuit Breaker Fail Timing

7SR210 & 7SR220 Applications Guide
10ms
20ms
50ms
40ms
120ms
120ms
10ms
50ms
20ms
60ms
CB Backtrip
Sucessful
200 220 240 260 280
Backtrip
Trip Relay
Operation
No Reset of
CBF elements
CBF Back trip
Operation
200 220 240 260 280
ms from fault
occuring
300 320 340
Operation of all
BB CB's
Reset of
CBF elements
ms from
occuri
300 320 340 360
Page 35 of 40