Output Clock; Interface Distribution; Spi Interface; Mcsi Interface - Hytera MD78X Service Manual

Baseband Section
4.3.2

Output Clock

The baseband outputs 3 clock signals fed to U231, U100 and Option Board respectively.
4.4

Interface Distribution

4.4.1

SPI Interface

SPI of U302 operates in Master Mode, and is controlled by MPU or DMA. In this case, U302 can
provide 4 chip select signals, of which CS2 is used to control the IF processor U701.
4.4.2

MCSI Interface

When U302 is communicating with U100, it works in Master Mode with clock frequency of up to
9.6MHz. U100 uses MCSI synchronization as chip select signal and MCSI1.DOUT as data cable to
configure its register.
4.4.3

MICROWIRE Interface

PE
PC
U701
PD

Figure 4-3 Diagram of SPI Interface

MCSI1.CLK
U302
MCSI1.DOUT
MSCI1.SYNC

Figure 4-4 Diagram of MCSI Interface

U302
UWIRE.SDO
UWIRE.SDI
UWIRE.SCLK
UWIRE.CS3

Figure 4-5 Diagram of MICROWIRE Interface

U302
SPIF.CS2
SPIF.SCK
SPIF.DOUT
Data
CLK
/CS
MOSI
MISO
U231
SCLK
/SS
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Service Manual
U100