HP ProLiant BL620c Generation 7 Quickspecs page 12

QuickSpecs
Standard Features
Pause Loop Exiting provides detection of spin locks in guest software and helps avoid lock-
holder preemption to reduce overhead and improve performance.
Intel® VT-d (Intel® Virtualization Technology for Directed I/O) enables the VMM to assign specific
I/O devices to specific guest OSs improving security and availability.
Mezzanine options and I/O Mezzanine options and I/O Mezzanine options and I/O Mezzanine options and I/O
Optional dual-port Fibre Channel mezzanine cards for redundant SAN connections.
Optional dual-port InfiniBand mezzanine cards for redundant high performance connections.
Four embedded Ethernet adapter ports for redundant LAN connections.
Multiple mezzanine I/O expansion slots each supported multiple data paths routed to redundant
interconnect modules.
Network Adapter Teaming (Bonding) provides network fault tolerance, transmit load balancing,
and switch-assisted load balancing.
Processor/Chipset Processor/Chipset Processor/Chipset Processor/Chipset
Processor Internal Sensors & Thermal Control protection against over-temperature conditions.
Cache parity/ECC protects cache data from accidental data corruption due to particle hits.
Machine Check Architecture (MCA) detects and captures hardware errors such as system bus,
ECC, parity, cache, other.
Enhanced MCA handling & error logging builds upon the original Machine Check Architecture to:
offers more "banks" and increased "resolution" for reporting errors that cause MCA events and 2)
sets check flags for the OS to poll.
External Bus Error Recovery (ECC) enables automatic correction from a single data bit error and
detection of double data error bits on the memory data bus.
Corrupt Data Containment tags faulty data before it is consumed (often called data poisoning) to
limit the impact to the currently running program and to greatly reduce the need to reset the
system.
On-Die Error Protection protects registers from particle hits.
Storage Storage Storage Storage
Two hot-plug SAS/SATA/SSD drive bays.
Integrated HP Smart Array P410i Controller with RAID 0 and 1 standard
Integrated HP Smart Array P410i Controller upgradeable firmware with recovery ROM capability
HP Smart Array P410i flash backed write cache (FBWC) options to 1GB.
Optional multiple Smart Array RAID mezzanine controllers (with BBWC and FBWC) for direct
attach and shared SAS storage external to the c-Class enclosure.
Optional HP D2200sb Storage Blade for direct attached and shared storage within the c-Class
enclosure.
Intel® QuickPath Interconnect (QPI) Intel® QuickPath Interconnect (QPI) Intel® QuickPath Interconnect (QPI) Intel® QuickPath Interconnect (QPI)
QPI Link Retry restarts as cycle when a failure is detected on the link.
QPI Clock Failover redirects the forwarded clock to one of the two failover clock lanes in the event
of a forwarded clock failure.
QPI Self-Healing enables a QPI link to map a failed lane and downshift from full to ½ width (or ½
width to ¼ width) QPI link if there are errors on the link.
QPI Cycle Redundancy Checking (CRC) automatically detects data errors using a checksum of
either 8 bits or 16 bits.
QPI Poisoning tags an erroneous packet with a "poisoned bit" on the QPI fabric.
QPI Lane Failover identifies a faulty lane within data paths removing them from operation
DA - 13747 Worldwide — Version 16 — September 26, 2011
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