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2-4 A 8-bit 16-bit timer, a peripheral initial
101: Timer 1 underflow
110: Prohibition of a setup
111: TMIN2 terminal input
TM3MD: Timer 3 mode register
Bit7 : Timer operation permission
0: Stop of operation
1: Initialization
Bit6 : Timer initialization
0: Usually, operation
1: Initialization
Bit5-3: Prohibition (0 fixation)
Bit2-0: Clock source selection
000:IOCLK
001:IOCLK/8
010:IOCLK/32
011: Cascade connection with a timer 2
100: Timer 0 underflow
101: Timer 1 underflow
110: Timer 0 underflow
111: TMIN3 terminal input
TM4MD: Timer 4 mode register
Bit7 : Timer operation permission
0: Stop of operation
1: Permission of operation
Bit6 : Timer initialization
0: Usually, operation
1: Initialization
Bit5-3: Prohibition (0 fixation)
Bit2-0: Clock source selection
000:IOCLK
001:IOCLK/8
010:IOCLK/32
011: Prohibition of a setup
100: Prohibition of a setup
101: Timer 5 underflow
The value of a base register is loaded to a binary counter.
The timer pulse output 3 is reset on a low level.
The value of a base register is loaded to a binary counter.
The timer pulse output 4 is reset on a low level.
2-32
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