Cpu (System Control) - Sanyo FC3G2 Training Manual

2. CPU (System Control)

The following firgure shows a block diagram of the CPU peripheral circuit. CPU that
use for FC3G2 is AC5G2 CPU.
BUS SDA
V/C IC
BUS SCL
IIC SDA
EEPROM
IIC SCL
Vss(GND)
CPU OSC input
(X'tal 32.768KHz)
CPU OSC output
VDD(+5V)
SECAM Killer Input
AFT signal input
S-Video input (Low: S-in)
panel key input
RESET input
Filter for PLL
(Connect to ground through CR)
CV input(no use=open)
Bilingual output
(Low:S-1,High:S-2)
V-sync signal input
H-sync signal input
NOTE : * N-ch.open drain output (Vout max.+5V)
TERMINAL ASSIGNMENT (AC5G2 CPU)
LC863448W-52F1-TLM (ROM:48Kbytes)
1 P10/SDA0
2 P11/SCLK0
3 P12/SDA1
4 P13/SCLK1
5 Vss
6 XT1
7 XT2
8 VDD
9 P04/AN4
10 P05/AN5
*
11 P06/AN6
12 P07/AN7
13 RESET
14 FILT
15 CVIN
16 P30
17 VS
18 HS
4
*
P03 36 Status input(factory)
(Low:factory mode)
P02 35 ACK output(factory)
(Low:factory mode)
*
P01 34 BASS output & Woofer Output
P00 33 VIF-M output
(High:NTSC,Low:other)
P17 32 ON timer LED on/off output
(Low:Timer on)
P16/PWM3 31 Power on/off output
(High:on)
P15/PWM2 30 Volume PWM output
P14/PWM1 29 Sound Mute output
(High:Mute ON)
P73/INT3 28 remote control signal input
P72/INT2 27 Power failure input
P71/INT1 26 TV/AV1/AV2/AV3
option output
P70/INT0 25 50/60 output (Low:60Hz)
(PAL:50Hz, NTSC:60Hz)
P32 24 TV/AV1/AV2/AV3
option output
P31 23 L/R or L/L
BLNK 22 OSD Blanking signal output
B 21 OSD Blue signal output
G 20 OSD Green signal output
R 19 OSD Red signal output
Training Manual FC3G2 Chassis