Sony STR-DG910 Service Manual page 73

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Pin No.
92
93
94 to 97 MA10, MA8, MA11, MA9
98
99
100
101
102
103
104
105
106
107
108
109
110 to 113 MD7, MD8, MD6, MD9
114
115
116 to 119 MD5, MD10, MD4, MD11
120
121
122 to 125 MD3, MD12, MD2, MD13
126
127
TE
L 13942296513
128
129 to 132 MD1, MD14, MD0, MD15
133
134 RFFO (CSB)
135
136
137
138
139
140
141 VPDX (CPOUT)
142 TEST6 (VCION
143
144
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Pin Name I/O
CVSS — Ground (for core)
OVDD — Power supply pin (+3.3 V) (for I/O)
O Address signal output for SD-RAM.
OVDD — Power supply pin (+3.3 V) (for I/O)
OVSS — Ground (for I/O)
RAS O Row address strobe signal output for SD-RAM.
DQM O Data mask signal output for SD-RAM.
CAS O Column address strobe signal output for SD-RAM.
MCLK O Serial data transfer clock signal output for SD-RAM.
WE O Write enable signal output for SD-RAM.
TEST3 I Test pin (Fixed at L in this set)
TEST4 I Test pin (Fixed at L in this set)
OVSS — Ground (for I/O)
OVDD — Power supply pin (+3.3 V) (for I/O)
CVDD — Power supply pin (+2.5 V) (for core)
I/O Two-way data bus with SD-RAM.
OVDD — Power supply pin (+3.3 V) (for I/O)
OVSS — Ground (for I/O)
I/O Two-way data bus with SD-RAM.
OVDD — Power supply pin (+3.3 V) (for I/O)
OVSS — Ground (for I/O)
I/O Two-way data bus with SD-RAM.
OVSS — Ground (for I/O)
CVSS — Ground (for core)
OVDD — Power supply pin (+3.3 V) (for I/O)
I/O Two-way data bus with SD-RAM.
MPU interface slave address setting pin. Slave address setting: 0X72 when SLV is "0",
SLV I
0X70 when SLV is "1".
O MPEG flag (repeat first field flag) signal output (Not used in this set)
I2C two-way data bus with HDMI receiver, HDMI transmitter, HDMI controller,
SDA I/O
video A/D converter and video encoder.
SCL I Serial data transfer clock signal input from HDMI controller.
SRN I System reset signal input from HDMI controller. (L: reset)
OVSS — Ground (for I/O)
CVDD — Power supply pin (+2.5 V) (for core)
PLL=VDD — Power supply pin (+2.5 V) (for PLL)
— Not used. (Open)
I Test pin (Fixed at L in this set)
PLL_GND — Ground (for I/O)
IVDD — Power supply pin (+3.3 V) (for I/O)
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Pin Description
1 5 0 5 8 2 9 9 4
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STR-DG910
9 9
2 8 9 9
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