Onkyo TX-SR674E Service Manual page 94

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -31
Q8001 : SII504 (I/P Video Converter)
TERMINAL DESCRIPTION (1/5)
Signal Group
Video Input
Video Output
Signal Name Notes Type
VidInData[9:2] 5V
VidInData[19:12] 5V/PD
(HostData[15:8])
VS 5V/PD
(HostData[7])
HS 5V/PD
(HostData[6])
VidInClk 5V
Red_Cr[9:0]
Green_Y[9:0]
Blue_Cb[9:0]
/HSync
/VSync
/CSync
/CBlank
LCDPwrEn
VidOutClk
Clk48M 5V
Description
In Multiplexed Video Input Data (ITU-R BT.656,
8-bit & H/V syncs formats); Y (luma) Video
Input Data (16-bit & H/V syncs format).
In Chroma Video Input Data (16-bit & H/V syncs
format only). See Host Interface pin list for
pin functions when not used for video input.
In Vertical Sync input (8/16-bit & H/V syncs
format only). See Host Interface pin list for
pin function when not used for video input.
In Horizontal Sync input (8/16-bit & H/V syncs
format only). See Host Interface pin list for
pin function when not used for video input.
In Video Input Clock, 27.0 MHz
Out Red Data (RGB output mode);
Cr Data (YCrCb output mode)
Out Green Data (RGB output mode);
Y Data (YCrCb output mode)
Out Blue Data (RGB output mode);
Cb Data (YCrCb output mode)
Out Horizontal Sync
Out Vertical Sync
Out Composite Sync
Out Composite Blank
Out LCD Power Enable
Out Video Output Clock, 36, 27 or 24 MHz
InOut 48 MHz Clock. Normally, this pin is a no-
connect, outputting an internal PLL-generated
48.0 MHz clock and receiving that same clock
through its input buffer. To bypass the PLL,
set /BypPLLClk48M = 0, and supply a 48.0
MHz clock to the Clk48M pin.
TX-SR674/674E/8467