Onkyo TX-SR674E Service Manual page 107

IC BLOCK DI AGRAMS AND TERMINAL DESCRIPTIONS -44
Q8101: ADV7401 (Multi-Format SDTV/HDTV Video Decoder)
TERMINAL DESCRIPTION (3/3)
Pin No. Mnemonic
15 SFL/SYNC_ O
UT
64 REFOUT
65 CML
61, 62 CAPY1–
CAPY2
68, 69 CAPC1–
CAPC2
67 BIAS
86 HS_IN/CS_IN
85 VS_IN
79 DE_IN
35 DCLK_IN
52 SOG
77 SOY
Type Function
O SFL (Subcarrier Frequency Lock); this pin contains a serial
output stream which can be used to lock the subcarrier
frequency when this decoder is connected to any Analog
Devices digital video encoder. SYNC_OUT is the sliced sync
output signal only available in CP mode.
O Internal voltage reference output.
O The CML pin is a common-mode level for the internal ADCs.
I ADC capacitor network.
I ADC capacitor network.
O BIAS is an external bias setting pin. Connect the
recommended resistor (1.35k ) between pin and ground.
I Can be configured in CP mode to be either a digital HS input
signal or a digital CS input signal used to extract timing in a
5-wire or 4-wire RGB mode.
I VS input signal used in CP mode for 5-wire timing mode.
I DE_IN is a data enable input signal used in 24-bit digital
input port mode, for example,
24-bit RGB data from a DVI Rx IC.
I DCLK_IN is a clock input signal used in 24-bit digital input
mode (e.g. 24-bit RGB data from a DVI Rx IC) and also in
digital CVBS input mode.
I SOG is a sync on green input used in embedded sync mode.
I SOY is a sync on luma input used in embedded sync mode.
TX-SR674/674E/8467 MD-2000