FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
& timer
CLK
CKE
CS
RAS
CAS
refresh
WE
UDQM
LDQM
Bank Select
A0
A1
A11
BA0
BA1
Internal Row
counter
Row
Row active
Pre
Decoders
Column
Column
Active
Pre
Decoders
Column Add
Counter
Address
Registers
Mode Registers
1Mx16 Bank 3
1Mx16 Bank 2
1Mx16 Bank 1
1Mx16 Bank 0
Memory
Y decoders
Burst
Counter
CAS Latency
Data Out Control
18
HY57V641620HG
Cell
Array
Pipe Line Control
DQ0
DQ1
DQ14
DQ15