Sony STR-DA4400ES Service Manual page 143

D-VIDEO BOARD IC3601 FLI8668-LF-BC (VIDEO PROCESSOR)
Pin No. Pin Name
A1 NC
A2 MSTR1_SDA
A3 MSTR1_SCL
A4, A5 FSDATA1, FSDATA3
A6 FSDQM0
FSDATA5, FSDATA7,
A7 to A10
FSDATA9, FSDATA11
A11 FSDQM1
A12, A13 FSDATA13, FSDATA15
A14 VDDA18_DLL
A15, A16 FSDATA17, FSDATA19
A17 FSDQS2
FSDATA21, FSDATA23,
A18 to A21
FSDATA25, FSDATA27
A22 FSDQS3
A23, A24 FSDATA29, FSDATA31
A25, A26 RPLL_AGND
B1 BDATA0
B2 OCM_UDO_1
B3 OCM_UDI_1
B4, B5 FSDATA0, FSDATA2
B6 FSDQS0
FSDATA4, FSDATA6,
B7 to B10
FSDATA8, FSDATA10
B11 FSDQS1
B12, B13 FSDATA12, FSDATA14
B14 VSSA18_DLL
B15, B16 FSDATA16, FSDATA18
B17 FSDQM2
FSDATA20, FSDATA22,
B18 to B21
FSDATA24, FSDATA26
B22 FSDQM3
B23, B24 FSDATA28, FSDATA30
B25 RPLL_DGND
B26 XTAL
C1 to C3 BDATA3 to BDATA1
C4 FSCKE
C5 FSCLKN
C6 to C8 FSADDR8 to FSADDR6
C9 FSVREF
FSADDR5, FSADDR12,
C10 to FSADDR9, FSADDR4,
C18 FSADDR11, FSADDR3
to FSADDR0
C19 FSVREF
C20, C21 FSBKSEL1, FSBKSEL0
C22 FSCS1
C23 FSWE
C24 FSRAS
C25 RPLL_1.8V
C26 TCLK
D1 BDATA6
D2, D3 BDATA5, BDATA4
D4 DDR_2.5V
D5 FSCLKP
D6 to D8 DDR_2.5V
D9 FSVREFVSS
D10 to
DDR_2.5V
D15
D16 FSADDR10
I/O
- Not used
O Power detection signal output to the video system controller
I Busy signal input from the video system controller
I/O Two-way data bus with the SD-RAM
O Lower data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Upper data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.8V)
I/O Two-way data bus with the SD-RAM
O Upper data strobe signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Lower data strobe signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Ground terminal
I Digital video signal (B) input from the OSD controller
O UART communication transfer data output to the video system controller
I UART communication transfer data input from the video system controller
I/O Two-way data bus with the SD-RAM
O Upper data strobe signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Lower data strobe signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Ground terminal
I/O Two-way data bus with the SD-RAM
O Lower data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Upper data mask signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Ground terminal
O System clock output terminal (19.6608 MHz)
I Digital video signal (B) input from the OSD controller
O Clock enable signal output to the SD-RAM
O Clock signal (negative) output to the SD-RAM
O Address signal output to the SD-RAM
O Reference voltage output to the SD-RAM
O Address signal output to the SD-RAM
O Reference voltage output to the SD-RAM
O Bank select signal output to the SD-RAM
O Chip select signal output terminal
O Write enable signal output to the SD-RAM
O Row address strobe signal output to the SD-RAM
- Power supply terminal (+1.8V)
I System clock input terminal (19.6608 MHz)
I Digital video signal input terminal
I Digital video signal (B) input from the OSD controller
- Power supply terminal (+2.5V)
O Clock signal (positive) output to the SD-RAM
- Power supply terminal (+2.5V)
- Ground terminal
- Power supply terminal (+2.5V)
O Address signal output to the SD-RAM
Description
Not used
Not used
STR-DA4400ES
143