Sony XAV-A1 Service Manual page 82

XAV-A1
MAIN BOARD IC861 HD64413 (GRAPHIC CONTROLLER)
Pin No.
Pin Name
1, 2
SD4, SD5
3
VCC
4 SD6
5
GND
6 to 11
SD7 to SD12
12
VCC
13 SD13
14
GND
15, 16
SD14, SD15
17
GND
18 to 24 SA1 to SA7
25
VCC
26
SA8
27
GND
28 to 37 SA9 to SA18
38
VCC
39
SA19
40
GND
41 to 43 SA20 to SA22
44
/RST 3
45 MODE0
46, 47 MODE1, MODE2
48 CLK0
49
MCLK
50
PLL VCC
51, 52 CAP1, CAP2
53 PLL GND
54, 55
MD0, MD1
56
VCC
57
MD2
58 GND
59, 60
MD3, MD4
61
GND
62, 63
MD5, MD6
64 VCC
65
MD7
66
GND
67 to 72
MD15 to MD10
73 VCC
74
MD9
75
GND
76
MD8
77
/MCS
78
/MWE
79, 80
LDQM0, LDQM1
81
UDQM0
82
I/O
I/O Two-way data bus with the CPU, SD-RAM and flash memory
- Power supply terminal (+3.3V)
I/O Two-way data bus with the CPU, SD-RAM and flash memory
- Ground terminal
I/O Two-way data bus with the CPU, SD-RAM and flash memory
- Power supply terminal (+3.3V)
I/O Two-way data bus with the CPU, SD-RAM and flash memory
- Ground terminal
I/O Two-way data bus with the CPU, SD-RAM and flash memory
- Ground terminal
I Address signal input from the CPU
- Power supply terminal (+3.3V)
I Address signal input from the CPU
- Ground terminal
I Address signal input from the CPU
- Power supply terminal (+3.3V)
I Address signal input from the CPU
- Ground terminal
I Address signal input from the CPU
I Reset signal input from the system controller "L": reset
I Mode setting terminal Fixed at "H" in this set
I Mode setting terminal Fixed at "L" in this set
I System clock signal input from the clock generator
O Clock signal output to the graphic memory
- Power supply terminal (+3.3V)
- External capacitor connection terminal
- Ground terminal
I/O Two-way data bus with the graphic memory
- Power supply terminal (+3.3V)
I/O Two-way data bus with the graphic memory
- Ground terminal
I/O Two-way data bus with the graphic memory
- Ground terminal
I/O Two-way data bus with the graphic memory
- Power supply terminal (+3.3V)
I/O Two-way data bus with the graphic memory
- Ground terminal
I/O Two-way data bus with the graphic memory
- Power supply terminal (+3.3V)
I/O Two-way data bus with the graphic memory
- Ground terminal
I/O Two-way data bus with the graphic memory
O Chip select signal output to the graphic memory
O Write enable signal output to the graphic memory
O Write mask signal output to the graphic memory (lower byte)
O Write mask signal output to the graphic memory (upper byte)
Description