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1. General description
2. Features
2.1 General features
TFA9812
BTL stereo Class-D audio amplifier with I
Rev. 02 — 22 January 2009
The TFA9812 is a high-efficiency Bridge Tied Load (BTL) stereo Class-D audio amplifier
2
with a digital I
S audio input. It is available in a HVQFN48 package with exposed die
paddle. The exposed die paddle technology enhances the thermal and electrical
performances of the device.
The TFA9812 features digital sound processing and audio power amplification. It supports
2
I
C control mode and Legacy mode. In Legacy mode I
because the key features are controlled by hardware pin connections.
A continuous time output power of 2
an external heat sink. Due to the implementation of a programmable thermal foldback
even for high supply voltages, higher ambient temperatures, and/or lower load
impedances, the device operates without sound interrupting behavior.
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence
required). It features various soft and hard impact protection mechanisms to ensure an
application that is both user friendly and robust.
A modulation technique is applied for the TFA9812, which supports common mode choke
approach (1 common mode choke only per BTL amplifier stage). This minimizes the
number of external components.
I
3.3 V and 8 V to 20 V external power supply
I
High efficiency and low power dissipation
I
Speaker outputs fully short circuit proof across load, to supply lines and ground
I
Pop noise free at power-up/power-down and sample rate switching
I
Low power Sleep mode
I
Overvoltage and undervoltage protection on the 8 V to 20 V power supply
I
Undervoltage protection on the 3.3 V power supply
I
Overcurrent protection (no audible interruptions)
I
Overdissipation protection
I
Thermally protected and programmable thermal foldback
I
Clock error protection
I
2
I
C mode control or Legacy mode (i.e. no I
I
2
Four different I
C addresses supported
I
Internal Phase-Locked Loop (PLL) without using external components
2
C involvement is not needed
12 W (R
= 8 , V
L
DDP
2
C) control
2
S input
Preliminary data sheet
= 15 V) is supported without
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Summary of Contents for NXP Semiconductors TFA9812
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Page 1: General Description
TFA9812 is designed in such a way that it starts up easily (no special power-up sequence required). It features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust. -
Page 2: Dsp Features
NXP Semiconductors No high system clock required (PLL is able to lock on BCK) No external heat sink required 5 V tolerant digital inputs Supports dual coil inductor application Easy application and limited external components required 2.2 DSP features Digital parametric 10-band equalizer... -
Page 3: Quick Reference Data
NXP Semiconductors 4. Quick reference data Table 1. Unless specified otherwise, V 24-bit I S input data, MCLK clock mode, typical application diagram Symbol General DDA(3V3) DDD(3V3) DDA(3V3) DDD(3V3) o(RMS) is the current through the analog supply voltage (V voltage (V... -
Page 4: Ordering Information
NXP Semiconductors 5. Ordering information Table 2. Ordering information Type number Package Name TFA9812HN HVQFN48 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Description plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 0.85 mm... -
Page 5: Block Diagram
DATA INTERFACE EQUALIZER MUTE POWERUP ENABLE GAIN PROTECTION CSEL ADSEL2/PLIM2 CONTROL INTERFACE ADSEL1/PLIM1 SCL/SFOR SDA/MS DIAG CDELAY Fig 1. TFA9812 block diagram AVOL DDD(3V3) DDA(3V3) TFA9812 CSEL CONTROLLER THERMAL FOLDBACK INTER- POLATION POWER GAIN FILTER AND LIMITER DE-EMPHASIS CONTROLLER REFERENCES... -
Page 6: Pinning Information
7. Pinning information 7.1 Pinning Fig 2. Table 3. TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I shows the block diagram of the TFA9812. For a detailed description of the audio Section 8.1. terminal 1 index area XTALIN XTALOUT... - Page 7 NXP Semiconductors Table 3. TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Pinning description TFA9812 …continued Symbol Type Description OUT2N Negative PWM output channel 2 BOOT1P Bootstrap high-side driver positive PWM output channel 1 OUT1P Positive PWM output channel 1...
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Page 8: Functional Description
These specific gain settings are related to maximum clip levels of < 0.5 %, 10 %, 20 % or 30 % THD at the TFA9812 output. These maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input signal. -
Page 9: Functional Modes
NXP Semiconductors The block control defines the operational control settings of the TFA9812 in line with the actual I The PLL block creates the system clock and can take the I external crystal as reference source. The following protections are built into the TFA9812: •... -
Page 10: S Master/Slave Modes And Mclk/Bck Clock Modes
S interface can be set in master or in slave. • In I circuit which uses an external crystal. The BCK, WS and MCLK signals are generated by the TFA9812. On the MCLK pin the TFA9812 delivers a master clock running at the crystal frequency. • In I –... - Page 11 NXP Semiconductors Table 6. Pin value CSEL Under these conditions the mode is enabled by the appropriate I In I S slave mode selection between BCK and MCLK clock modes is automatic. MCLK clock mode is given higher priority than BCK. If the MCLK clock is judged valid by the protection circuit then MCLK clock mode is enabled.
- Page 12 NXP Semiconductors Table 8. Control mode Legacy Table 9. Control mode Legacy The valid sample frequencies are shown in TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Valid MCLK frequencies in I S slave mode (kHz) 44.1...
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Page 13: Power-Up/Power-Down
NXP Semiconductors 8.3 Power-up/power-down external voltage supplies POWERUP ENABLE available soft mute setting in C mode AVOL pin in Legacy mode outputs Operating mode active Fig 3. 8.3.1 Power-up Figure 3 for initiating a power-up reset. Table 10. Symbol wake... -
Page 14: Power-Down
Figure 3 power-down. Table 11. Power-up pin value Putting the TFA9812 into power-down is equivalent to enabling Sleep mode (see Section required. In order to prevent audible clicks, soft mute should be enabled at least T seconds before enabling Sleep mode. - Page 15 NXP Semiconductors Table 12. BCK frequency Interface format (MSB first) 48 f 48 f 48 f 48 f 64 f 64 f 64 f 64 f 64 f 64 f Remark: Only MSB-first formats are supported. LEFT DATA LEFT DATA...
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Page 16: Digital Audio Data Format Control
NXP Semiconductors In I C control mode the following sample frequency f 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz or 192 kHz. The I... - Page 17 Each band filter can be programmed to perform a band-suppression (G < 1) or a band-amplification (G > 1) function around the center frequency. Each band of the TFA9812 equalizer has a second-order Regalia-Mitra all-pass filter structure. The structure is shown in Fig 5.
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Page 18: Equalizer Band Control
NXP Semiconductors The ranges of the TFA9812 parametric equalizer settings for each band are: • The Gain, G is from 30 dB to +12 dB. • The center frequency, f • The quality factor Q is from 0.001 to 8. - Page 19 NXP Semiconductors Equation example, in word2 bits [14:8] = [0111 010] represent k Table 15. Word word1 word1 word1 word2 word2 word2 word2 word2 Section 9.5.4 equalizer. Fig 6. TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I –...
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Page 20: Digital Volume Control
NXP Semiconductors Gain (dB) Fig 7. Gain (dB) Fig 8. 8.5.2 Digital volume control In I C control mode both audio channels have separate digital volume control. In Legacy control mode the volume control of both channels is common and the volume control setting depends on the supply voltage on the pin AVOL (32). -
Page 21: Soft Mute And Mute
C control for the polarity switch can be found in 8.5.5 Gain boost and clip level control An additional gain boost of +24 dB can be selected in the TFA9812. In Legacy mode this feature can be selected with the GAIN pin, see... -
Page 22: Output Power Limiter
In I The TFA9812 features also specific gain settings which are related to < 0.5 %, 10 %, 20 % or 30 % clipping at the output of the TFA9812. These clipping values are only valid under the following conditions: •... -
Page 23: Class-D Amplification
Can be overruled by a forced 3-state in Sleep or Fault mode. 8.7 Protection mechanisms The TFA9812 has a wide range of protection mechanisms to facilitate optimal and safe application. All of these are active in both I The following protections are included in the TFA9812: •... -
Page 24: Thermal Foldback
Section 8.7.2 Overtemperature protection This is a ‘hard’ protection to prevent heat damage to the TFA9812. The overtemperature threshold level is the 160 C junction temperature. When the threshold temperature is exceeded the output stages are set to 3-state mode. -
Page 25: Overdissipation Protection
Section 8.7.8 Lock protection When the selected clock input source (MCLK, BCK or crystal) stops running, the TFA9812 is able to detect this and set the output stages to 3-state mode. Without this protection peripheral devices in an application might be damaged. -
Page 26: Invalid Bck Protection
Symbol Conditions TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I . If it is not at one of these frequencies the TFA9812 will set the output stages shows the overview of the protections. Overview protections DIAG programmable Floating max. -
Page 27: I 2 C Bus Interface And Register Settings
9.1 I C bus interface The TFA9812 supports the 400 kHz I can be used to control the TFA9812 and to exchange data with it when in I mode, see The TFA9812 can operate in I The serial hardware interface involves the pins of the TFA9812 as described in Table 22. -
Page 28: C Write Cycle Description
The cycle format for writing to the TFA9812 using SDA is as follows: 1. The microcontroller asserts a start condition (S). 2. The microcontroller sends the device address (7 bits) of the TFA9812 followed by the R/!W bit set to 0. -
Page 29: Top-Level Register Map
NXP Semiconductors 9. The TFA9812 sends the first byte. This is the most significant byte of the register. 10. The microcontroller asserts an acknowledge. 11. The TFA9812 sends the second byte. 12. The microcontroller asserts either an acknowledge or a negative acknowledge (NA). - Page 30 Equalizer_D4 word_2 Equalizer_A5 word_1 Equalizer_A5 word_2 Equalizer_B5 word_1 Equalizer_B5 word_2 Equalizer_C5 word_1 Equalizer_C5 word_2 Equalizer_D5 word_1 Equalizer_D5 word_2 PWM signal control Digital-in clock configuration Thermal foldback control TFA9812 temperature Miscellaneous status © NXP B.V. 2009. All rights reserved. 30 of 66...
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Page 31: Interpolator Settings And Soft Mute
NXP Semiconductors 9.5.1 Interpolator settings and soft mute Table 28. Register address 00h: miscellaneous I Symbol Default Symbol INV_POL Default Table 29. 5 to 4 3 to 1 9.5.2 Volume control Table 30. Register address 01h: volume control Symbol VOL_L7... -
Page 32: Digital Input Format
NXP Semiconductors Table 31. 15 to 8 7 to 0 9.5.3 Digital input format Table 32. Register address 02h: digital input format Symbol Default Symbol Default Table 33. 3 to 1 9.5.4 Equalizer configuration Table 34. Register address 03h: equalizer configuration... -
Page 33: Equalizer Settings
NXP Semiconductors Table 35. 9.5.5 Equalizer settings Table 36. Register addresses xxh = 04, 06...2A For word1 for equalizer 'yy' see Figure 9 Symbol Eyy_t Eyy_k Default Symbol Eyy_k Eyy_k Default Default settings are shown in Table Table 37. Register addresses xxh = 05, 07...2B... - Page 34 NXP Semiconductors Left in Right in Fig 9. Equalizer configuration and register location mapping Table 38. 14 to 4 3 to 0 Table 39. 14 to 11 10 to 8 7 to 1 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Bit description of registers xxh = 04, 06...2A...
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Page 35: Pwm Signal Control
NXP Semiconductors Table 40. Default configuration equalizer for f Band A1/B1 A2/B2 Frequency (Hz) Q-factor Gain (dB) 9.5.6 PWM signal control Table 41. Register 2Ch: PWM signal control Symbol Default Symbol PLIM1 Default Table 42. 6 to 5 3 to 2... -
Page 36: Digital-In Clock Configuration
BTL stereo Class-D audio amplifier with I FSUB3 Bit description of register 2Dh:digital-in clock configuration Symbol Description FSUB[3:0] Sample frequency f DI_MS TFA9812 digital-in Master/Slave mode selection: TP_THR5 TP_THR4 Rev. 02 — 22 January 2009 FSUB2 FSUB1 FSUB0 of digital-in signal: 0 = 8 kHz 1 = 11.025 kHz... -
Page 37: Tfa9812 Temperature
TEMP5 TEMP4 Bit description of register 2Dh: digital-in clock configuration Symbol Description TEMP[9:0] Temperature of the TFA9812, which can be calculated in UVP1V8 Bit description of register 30h: miscellaneous status Symbol Description PLL frequency-over-range indicator: PLL frequency under-range indicator:... -
Page 38: Overview Of Functional Control In Each Control Mode
Table 51 functions described in description of each function. Table 51. D = fixed control setting, determined by default I supported (i.e. all options implemented in the TFA9812). Control function C register content Sleep mode enable Operating mode enable 3-state mode enable... -
Page 39: Internal Circuitry
NXP Semiconductors Table 51. D = fixed control setting, determined by default I supported (i.e. all options implemented in the TFA9812). Control function Clip level control Output power limit level control PWM signal frequency selection Thermal foldback threshold temperature control 32 kHz, 44.1 kHz and 48 kHz supported... - Page 40 NXP Semiconductors Table 52. 10/11 18/19 26/27 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Internal circuitry …continued Symbol Equivalent circuitry STABA STABD REFA TEST1 STAB2 STAB1 SSP2 SSP1 BOOT2N BOOT1P BOOT2P BOOT1N Rev. 02 — 22 January 2009...
- Page 41 NXP Semiconductors Table 52. 13/14 16/17 20/21 23/24 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Internal circuitry …continued Symbol Equivalent circuitry OUT2N OUT1P OUT2P OUT1N DIAG CDELAY POWERUP ENABLE GAIN CSEL ADSEL2/PLIM2 ADSEL1/PLIM1 TEST2 Rev. 02 — 22 January 2009...
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Page 42: Limiting Values
NXP Semiconductors Table 52. 11. Limiting values Table 53. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter analog supply voltage power supply voltage analog supply voltage (3.3 V) DDA(3V3) digital supply voltage (3.3 V) -
Page 43: Thermal Characteristics
NXP Semiconductors Table 53. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter voltage on pin x electrostatic discharge voltage = REFA = REFD 12. Thermal characteristics Table 54. Symbol th(j-a) th(j-c) th(j-lead) Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7). -
Page 44: Characteristics
NXP Semiconductors 13. Characteristics 13.1 DC Characteristics Table 55. DC characteristics Unless specified otherwise, V = REFD = REFA = 0 V, T MCLK clock mode, typical application diagram Symbol Parameter Supply voltage analog supply voltage power supply voltage analog supply DDA(3V3) voltage (3.3 V) - Page 45 NXP Semiconductors Table 55. DC characteristics …continued Unless specified otherwise, V = REFD = REFA = 0 V, T MCLK clock mode, typical application diagram Symbol Parameter HIGH-level output voltage LOW-level output voltage load capacitance SDA/MS, SCL/SFOR pin HIGH-level input...
- Page 46 NXP Semiconductors Table 55. DC characteristics …continued Unless specified otherwise, V = REFD = REFA = 0 V, T MCLK clock mode, typical application diagram Symbol Parameter Thermal Foldback (TF) thermal foldback act(th_fold) activation temperature OverTemperature Protection (OTP) thermal protection...
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Page 47: Ac Characteristics
NXP Semiconductors 13.2 AC characteristics Table 56. AC characteristics Unless specified otherwise, V = 1 kHz, f = 44.1 kHz, f = 400 kHz, 24-bit I Symbol Parameter Output power per channel RMS output power o(RMS) Performance THD+N total harmonic... -
Page 48: Timing
NXP Semiconductors Table 56. AC characteristics …continued Unless specified otherwise, V = 1 kHz, f = 44.1 kHz, f = 400 kHz, 24-bit I Symbol Parameter propagation delay PWM output rise time fall time minimum pulse width w(min) drain-source on-state resistance... -
Page 49: Application Information
NXP Semiconductors Table 57. Characteristics I C bus interface; see = 2.7 V to 3.6 V; V DDD(3V3) DDA(3V3) unless otherwise specified. Symbol Parameter set-up time for STOP condition SU;STO bus free time between a STOP and START condition data set-up time SU;DAT... -
Page 50: Output Current Limiting
NXP Semiconductors = Maximum duty factor (0.96). The output power at 10 % THD can be estimated using (10%) Figure 11 THD = 10 % as a function of BTL supply voltage for different load impedances. (0.5 %) (W/channel) (1) 6... -
Page 51: Speaker Configuration And Impedance
NXP Semiconductors Remark: A 4.8 used up to a supply voltage of 17 V without running into current limiting. Current limiting (clipping) will avoid audio holes, but it causes a distortion comparable to voltage clipping. 14.3 Speaker configuration and impedance For a flat-frequency response (second-order Butterworth filter) it is necessary to change... -
Page 52: I S Slave Mode And Legacy Control Mode
S slave mode and Legacy control mode C DELAY C STAB 1 nF 100 nF 30 29 OUT1N OUT1N BOOT2P OUT2P OUT2P TFA9812 OUT1P OUT1P BOOT1P OUT2N OUT2N C STAB C VPA C STAB 100 nF 100 nF 100 nF... -
Page 53: S Slave Mode And I C Control Mode
C control mode POWER IN C STAB C DELAY 1 nF 100 nF 30 29 OUT1N OUT1N BOOT2P OUT2P OUT2P TFA9812 OUT1P OUT1P BOOT1P OUT2N OUT2N C STAB C VPA C STAB 100 nF 100 nF 100 nF C control mode... -
Page 54: I 2 S Master Mode And Legacy Control Mode
S master mode and Legacy control mode C DELAY C STAB 1 nF 100 nF 30 29 OUT1N OUT1N BOOT2P OUT2P OUT2P TFA9812 OUT1P OUT1P BOOT1P OUT2N OUT2N 7 8 9 10 11 R STABA C STAB C VPA C STAB... -
Page 55: I 2 S Master Mode And I 2 C Control Mode
C control mode POWER IN C DELAY C STAB 1 nF 100 nF 30 29 OUT1N OUT1N BOOT2P OUT2P OUT2P TFA9812 OUT1P OUT1P BOOT1P OUT2N OUT2N 7 8 9 10 11 R STABA C STAB C VPA C STAB 100 nF... -
Page 56: Curves Measured In Typical Application
NXP Semiconductors 14.5 Curves measured in typical application THD+N (1) f = 6 kHz (2) f = 1 kHz (3) f = 100 Hz a. V = 12 V; R THD+N (1) f = 6 kHz (2) f = 1 kHz... - Page 57 NXP Semiconductors THD+N a. V = 12 V; R 6 ; P Fig 18. Total harmonic distortion-plus-noise as a function of frequency (dB) = 12 V; P = 1 W (1) R 15 H / 680 F (2) R 15 H / 680 F Fig 19.
- Page 58 NXP Semiconductors SVRR (dB) = 12 V; V = 500 mV (RMS) reference to ground; ripple No input signal (1) R (2) R Fig 21. SVRR as a function of frequency (W/chan.) a. V = 15 V; R (1) T...
- Page 59 NXP Semiconductors (W/chan.) (1) Power limiter = 0 dB (2) Power limiter = 1.5 dB (3) Power limiter = 3 dB (4) Power limiter = 4.5 dB a. V = 12 V; R 6 ; f (W/chan.) (1) Power limiter = 0 dB (2) Power limiter = 1.5 dB...
- Page 60 NXP Semiconductors = 12 V; f = 1 kHz; Power dissipation in junction only (1) R (2) R Fig 25. Power dissipation as a function of output power = 12 V; P = 1 W (1) R (2) R Fig 27. Channel separation as a function of frequency...
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Page 61: Package Outline
NXP Semiconductors 15. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) UNIT 0.05... -
Page 62: Handling Information
TFA9812 NXP Semiconductors BTL stereo Class-D audio amplifier with I S input 16. Handling information It is advisable to abide by the normal precautions appropriate to handling MOS devices. TFA9812_2 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. -
Page 63: Revision History
NXP Semiconductors 17. Revision history Table 59. Revision history Document ID Release date TFA9812_2 20090122 • Modifications: Table 55 “DC characteristics” TFA9812_1 2008/10/30 TFA9812_2 Preliminary data sheet BTL stereo Class-D audio amplifier with I Data sheet status Change notice Preliminary data sheet maximum value updated. -
Page 64: Contact Information
For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. -
Page 65: Table Of Contents
Thermal foldback control ....36 9.5.9 TFA9812 temperature ....37 9.5.10 Miscellaneous status . - Page 66 NXP Semiconductors 18.4 Trademarks ......64 Contact information..... 64 Contents .
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