Sharp LC-32GD8EE Service Manual page 96

LC-26GA5E
LC-32/37GD8E/RU
LC-32GA5E
LC-32/37BT8E/RU
Pin list
2.6.3. Pin Description (Continued)
Table 22: Port 2 PIO signal assignments
Port 2 bit Input
Bit 0
Bit 1
Bit 2
MAFE_DIN or ASC4_RXD
Bit 3
MAFE_FS or NOT_ASC4_CTS
Bit 4 MAFE_SCLK
Bit 5 PWM_CAPTURE0
Bit 6
Bit 7
a. Controlled by bit MAFE_OR_UART4_SEL in interconnect register CONFIG_CONTROL_D
(bit 20).
Table 23: Port 3 PIO signal assignments
Port 3 bit Input
Bit 0 SSC0_MTSR_DIN or SSC0_MRST_DIN
Bit 1 SSC0_SCLKIN
Bit 2 SSC1_MTSR_DIN or SSC1_MRST_DIN
Bit 3 SSC1_SCLK
Bit 4 NOT_CD_REQ[0] or PCMI_LRCLK
Bit 5 Slave mode I1284HOSTLOGICHIGH or
PCMI_DATA
Bit 6 NOT_CD_REQ[1] or PCMI_SCLK
Bit 7
a. Output function selected by bit 24 in interconnect configuration register
CONFIG_CONTROL_B (COMMS_SSC0_DOUT_MRST_NOTMTSR_MUXSEL)
b. Output function selected by bit 25 in interconnect configuration register
CONFIG_CONTROL_B (COMMS_SSC1_DOUT_MRST_NOTMTSR_MUXSEL)
38/709 STMicroelectronics Confidential
Output
MAFE_HC1 or NOT_ASC4_RTS
MAFE_DOUT or ASC4_TXD
a
a
PWM_COMPARE0
PWM_OUT0
Output
SSC0_MTSR_DOUT or SSC0_MRST_DOUT
SSC0_SCLKOUT
SSC1_MTSR_DOUT or SSC1_MRST_DOUT
SSC1_SCLK
I1284PERILOGICHIGH
Master mode I1284HOSTLOGICHIGH
I1284INNOTOUT
PWM_OUT1
96
7368868E
STi5516
a
a
a
b