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LVDS_PS8625
5
3.3VS
L69
L69
3.3VS
L70
L70
HCB1005KF-121T20
HCB1005KF-121T20
HCB1005KF-121T20
HCB1005KF-121T20
VDDIO_LVDS
VDDIOX_LVDS
C774
C774
C775
C775
C776
C776
0.47u_10V_Y5V_04
0.47u_10V_Y5V_04
10u_6.3V_X5R_04
10u_6.3V_X5R_04
0.47u_10V_Y5V_04
0.47u_10V_Y5V_04
GND_LVDS
D
1. Place the switching regulator inductor (L3) close to SW_OUT Pins (Pin15, Pin16).
2. The SW_OUT output traces should be as wide as possible.
3. The GNDX pins (Pin17, Pin18) should be connected to the main PCB ground plane, with the device GND pins of the PS8625 connected to separate GND island (GNDA) for the device.
The GND island (GNDA) should be connected to the main GND plane (GND) with a single-point connection by use of a wide PCB trace.
4. Place the 4.7uF decoupling Capacitor (C4) for VDDIOX close to VDDIOX pin.
5. The GND of the 4.7uF capacitor (C4) for VDDIOX should be placed close to the GND of 4.7uF capacitor (C5) behind Inductor.
6. Place the bead (L2) for VDDIOX close to PS8625.
R767
R767
*28mil_06
*28mil_06
single PCB trace
GND_LVDS
C
STUFF FOR LVDS
R770
R770
1K_04
1K_04
EDP_HPD_R
8
EDP_HPD
EDP_AUXN
C785
C785
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DAUXn
2
EDP_AUXN
EDP_AUXP
C786
C786
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DAUXp
2
EDP_AUXP
EDP_TXN_0
C789
C789
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX0n
2
EDP_TXN_0
EDP_TXP_0
C790
C790
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX0p
2
EDP_TXP_0
B
EDP_TXN_1
C791
C791
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX1n
2
EDP_TXN_1
EDP_TXP_1
C792
C792
0.1u_10V_X7R_04
0.1u_10V_X7R_04
DRX1p
2
EDP_TXP_1
L_BRIGHTNESS_R
R772
R772
0_04
0_04
PWM_IN
8
L_BRIGHTNESS_R
R776
R776
*0_04
*0_04
25
BRIGHTNESS
R777
R777
*100K_04
*100K_04
STUFF FOR EDP
L_BRIGHTNESS_R
R780
R780
*0_04
*0_04
PWMO
EDP_AUXN
R781
R781
*0_04
*0_04
DP_AUX#
15
EDP_AUXP
R785
R785
*0_04
*0_04
DP_AUX
15
A
EDP_TXN_0
R786
R786
*0_04
*0_04
DP_TXN0
15
EDP_TXP_0
R787
R787
*0_04
*0_04
DP_TXP0
15
EDP_TXN_1
R788
R788
*0_04
*0_04
DP_TXN1
15
EDP_TXP_1
R789
R789
*0_04
*0_04
DP_TXP1
15
5
4
3
L71
L71
L72
L72
BCNR3010C-2R2M
BCNR3010C-2R2M
HCB1005KF-121T20
HCB1005KF-121T20
SW_OUT
VDD12
VDDRX_LVDS
1
2
EVT
(
)
C777
C777
C778
C778
C779
C779
C780
C780
4.7u_6.3V_X5R_06
4.7u_6.3V_X5R_06
4.7u_6.3V_X5R_06
4.7u_6.3V_X5R_06
*4.7u_6.3V_X5R_06
*4.7u_6.3V_X5R_06
1u_6.3V_X5R_04
1u_6.3V_X5R_04
GND_LVDS
GND_LVDS
Note:
The decoupling caps shall be close
to the power pins as possible
C781
C781
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
GND_LVDS
U13
U13
DAUXn
1
DAUXn
DAUXp
2
DAUXp
Note:
3
GND_LVDS
GND
The decoupling caps shall be close
DRX0p
4
DRX0p
DRX0n
to the power pins as possible
5
DRX0n
VDDRX_LVDS
6
VDDRX
DRX1p
7
PS8625
PS8625
DRX1p
DRX1n
8
DRX1n
C783
C783
C784
C784
RST#_LVDS
9
RST#
PD#_LVDS
10
PD#
ENPVCC/I2C_ADDR
10u_6.3V_X5R_04
10u_6.3V_X5R_04
0.01u_16V_X7R_04
0.01u_16V_X7R_04
EDP_HPD_R
11
HPD
PWMO
12
PWMO
VDDIOX_LVDS
13
VDDIOX
VDDIOX_LVDS
14
VDDIOX
GND_LVDS
GND_LVDS
57
GND_LVDS
Epad
C793
C793
C794
C794
Note:
The decoupling caps shall be close
to the power pins as possible
GND_LVDS
GND_LVDS
25
SMC_EDP_CLK
25
SMD_EDP_DAT
4
3
2
LVDS_PLVDD_EN
ENBLT
PWMO
LVDS-L0N
LVDS-L0P
LVDS-L1N
Single link
LVDS-L1P
LVDS
LVDS-L2N
LVDS-L2P
LVDS-LCLKN
LVDS-LCLKP
LVDS-U0N
LVDS-U0P
LVDS-U1N
LVDS-U1P
LVDS-U2N
LVDS-U2P
LVDS-UCLKN
LVDS-UCLKP
P_DDC_CLK
P_DDC_DATA
To LVDS Connector
LVDS-U0N
42
TA1n
41
LVDS-U0P
Note:
TA1p
LVDS-U1N
40
The decoupling caps shall be close
TB1n
39
LVDS-U1P
to the power pins as possible
TB1p
VDDIO_LVDS
38
VDDIO
LVDS-U2N
37
TC1n
36
LVDS-U2P
C782
C782
TC1p
LVDS-UCLKN
35
TCK1n
34
LVDS-UCLKP
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
TCK1p
LVDS_PLVDD_EN
33
32
TD1n
31
GND_LVDS
TD1p
P_DDC_DATA
R768
R768
30
DDC_SDA
29
P_DDC_CLK
DDC_SCL
10K_04
10K_04
C787
C787
6-03-08625-030
1u_6.3V_X5R_04
1u_6.3V_X5R_04
Noe:
R13: LVDS output swing control
4.99K for default swing, change
Power On Configuration
the value for swing adjust
R774
R774
*4.7K_04
*4.7K_04
RLV_CFG
R775
R775
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K
L: 8-bit LVDS, VESA mapping
M: 8-bit LVDS, JEIDA mapping
H: 6-bit LVDS, both VESA and JEIDA mapping
EVT
for LVDS Panel
R778
R778
*4.7K_04
*4.7K_04
R779
R779
GND_LVDS
RLV_LNK/GPIO0
3.3VS
RLV_LNK: LVDS single link or dual link selection, internal pull-down ~80K
L: Single link LVDS
H: Dual link LVDS
R782
R782
R783
R783
LVDS_PLVDD_EN
R784
R784
*4.7K_04
*4.7K_04
4.7K_04
4.7K_04
4.7K_04
4.7K_04
I2C_ADDR: I2C Slave address selection, internal pull-down ~80K
L: 0x10h~0x1Fh
SMC_EDP_CLK
H: 0x90h~0x9Fh
SMD_EDP_DAT
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[16] LVDS_PS8625
[16] LVDS_PS8625
[16] LVDS_PS8625
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W3300-D03A
6-71-W3300-D03A
6-71-W3300-D03A
2,4..8,10,13..15,17..21,24,25,27..29,32
3.3VS
Custom
Custom
Custom
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date:
Date:
Date:
Friday, July 25, 2014
Friday, July 25, 2014
Friday, July 25, 2014
2
Schematic Diagrams
1
LVDS_PLVDD_EN
15
ENBLT
15
PWMO
15
LVDS-L0N
15
LVDS-L0P
15
D
LVDS-L1N
15
LVDS-L1P
15
LVDS-L2N
15
LVDS-L2P
15
LVDS-LCLKN
15
LVDS-LCLKP
15
Dual link
LVDS
LVDS-U0N
15
LVDS-U0P
15
LVDS-U1N
15
LVDS-U1P
15
Sheet 16 of 41
LVDS-U2N
15
LVDS-U2P
15
LVDS-UCLKN
15
LVDS_PS8625
LVDS-UCLKP
15
P_DDC_CLK
15
P_DDC_DATA
15
C
R769
R769
10K_04
10K_04
C788
C788
2.2u_6.3V_X5R_04
2.2u_6.3V_X5R_04
B
4.7K_04
4.7K_04
VDDIO_LVDS
4.7K_04
4.7K_04
VDDIO_LVDS
VDDIO_LVDS
A
Rev
Rev
Rev
1.0
1.0
1.0
Sheet
Sheet
Sheet
16
16
16
of
of
of
41
41
41
1
LVDS_PS8625 B - 17
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