Table of Contents
Advertisement
Schematic Diagrams
Haswell ULT DDR Channel-A/B
13
M_A_DQ[63:0]
D
Sheet 3 of 41
Haswell ULT DDR
C
Channel-A/B
B
A
B - 4 Haswell ULT DDR Channel-A/B
5
4
CHANNEL A
HSW_ULT_DDR3L
HSW_ULT_DDR3L
U29C
U29C
M_A_DQ0
AH63
AU37
SA_DQ0
SA_CLK#0
M_A_DQ1
AH62
AV37
SA_DQ1
SA_CLK0
M_A_DQ2
AK63
AW36
SA_DQ2
SA_CLK#1
M_A_DQ3
AK62
AY36
SA_DQ3
SA_CLK1
M_A_DQ4
AH61
SA_DQ4
M_A_DQ5
AH60
AU43
SA_DQ5
SA_CKE0
M_A_DQ6
AK61
AW43
SA_DQ6
SA_CKE1
M_A_DQ7
AK60
AY42
SA_DQ7
SA_CKE2
M_A_DQ8
AM63
AY43
SA_DQ8
SA_CKE3
M_A_DQ9
AM62
SA_DQ9
M_A_DQ10
AP63
AP33
SA_DQ10
SA_CS#0
M_A_DQ11
AP62
AR32
SA_DQ11
SA_CS#1
M_A_DQ12
AM61
SA_DQ12
M_A_DQ13
AM60
AP32
SA_DQ13
SA_ODT0
M_A_DQ14
AP61
SA_DQ14
M_A_DQ15
AP60
AY34
SA_DQ15
SA_RAS
M_A_DQ16
AP58
AW34
SA_DQ16
SA_WE
M_A_DQ17
AR58
AU34
SA_DQ17
SA_CAS
M_A_DQ18
AM57
SA_DQ18
M_A_DQ19
AK57
AU35
SA_DQ19
SA_BA0
M_A_DQ20
AL58
AV35
SA_DQ20
SA_BA1
M_A_DQ21
AK58
AY41
SA_DQ21
SA_BA2
M_A_DQ22
AR57
SA_DQ22
M_A_DQ23
AN57
AU36
SA_DQ23
SA_MA0
M_A_DQ24
AP55
AY37
SA_DQ24
SA_MA1
M_A_DQ25
AR55
AR38
SA_DQ25
SA_MA2
M_A_DQ26
AM54
AP36
SA_DQ26
SA_MA3
M_A_DQ27
AK54
AU39
SA_DQ27
SA_MA4
M_A_DQ28
AL55
AR36
SA_DQ28
SA_MA5
M_A_DQ29
AK55
AV40
SA_DQ29
SA_MA6
M_A_DQ30
AR54
AW39
SA_DQ30
SA_MA7
M_A_DQ31
DDR CHANNEL A
DDR CHANNEL A
AN54
AY39
SA_DQ31
SA_MA8
M_A_DQ32
AY58
AU40
SA_DQ32
SA_MA9
M_A_DQ33
AW58
AP35
SA_DQ33
SA_MA10
M_A_DQ34
AY56
AW41
SA_DQ34
SA_MA11
M_A_DQ35
AW56
AU41
SA_DQ35
SA_MA12
M_A_DQ36
AV58
AR35
SA_DQ36
SA_MA13
M_A_DQ37
AU58
AV42
SA_DQ37
SA_MA14
M_A_DQ38
AV56
AU42
SA_DQ38
SA_MA15
M_A_DQ39
AU56
SA_DQ39
M_A_DQ40
AY54
AJ61
SA_DQ40
SA_DQSN0
M_A_DQ41
AW54
AN62
SA_DQ41
SA_DQSN1
M_A_DQ42
AY52
AM58
SA_DQ42
SA_DQSN2
M_A_DQ43
AW52
AM55
SA_DQ43
SA_DQSN3
M_A_DQ44
AV54
AV57
SA_DQ44
SA_DQSN4
M_A_DQ45
AU54
AV53
SA_DQ45
SA_DQSN5
M_A_DQ46
AV52
AL43
SA_DQ46
SA_DQSN6
M_A_DQ47
AU52
AL48
SA_DQ47
SA_DQSN7
M_A_DQ48
AK40
SA_DQ48
M_A_DQ49
AK42
AJ62
SA_DQ49
SA_DQSP0
M_A_DQ50
AM43
AN61
SA_DQ50
SA_DQSP1
M_A_DQ51
AM45
AN58
SA_DQ51
SA_DQSP2
M_A_DQ52
AK45
AN55
SA_DQ52
SA_DQSP3
M_A_DQ53
AK43
AW57
SA_DQ53
SA_DQSP4
M_A_DQ54
AM40
AW53
SA_DQ54
SA_DQSP5
M_A_DQ55
AM42
AL42
SA_DQ55
SA_DQSP6
M_A_DQ56
AM46
AL49
SA_DQ56
SA_DQSP7
M_A_DQ57
AK46
SA_DQ57
M_A_DQ58
AM49
AP49
SA_DQ58
SM_VREF_CA
M_A_DQ59
AK49
AR51
SA_DQ59
SM_VREF_DQ0
M_A_DQ60
AM48
AP51
SA_DQ60
SM_VREF_DQ1
M_A_DQ61
AK48
SA_DQ61
M_A_DQ62
AM51
SA_DQ62
M_A_DQ63
AK51
SA_DQ63
3 OF 19
3 OF 19
V_DDR_WR_VREF01
DIMM
V_VCCDDQ
R330
R330
1.82K_1%_04
1.82K_1%_04
R329
R329
0_04
0_04
R326
R326
2.2_1%_06
2.2_1%_06
MVREF_DQ_DIMMA
R335
R335
C334
C334
1.82K_1%_04
1.82K_1%_04
0.022u_16V_X7R_04
0.022u_16V_X7R_04
R334
R334
24.9_1%_04
24.9_1%_04
5
4
3
U29D
U29D
14
M_B_DQ[63:0]
M_A_CLK_DDR#0
13
M_B_DQ0
AY31
M_A_CLK_DDR0
13
SB_DQ0
M_B_DQ1
AW31
M_A_CLK_DDR#1
13
SB_DQ1
M_B_DQ2
AY29
M_A_CLK_DDR1
13
SB_DQ2
M_B_DQ3
AW29
SB_DQ3
M_B_DQ4
AV31
M_A_CKE0
13
SB_DQ4
M_B_DQ5
AU31
M_A_CKE1
13
SB_DQ5
M_B_DQ6
AV29
SB_DQ6
M_B_DQ7
AU29
SB_DQ7
M_B_DQ8
AY27
SB_DQ8
M_B_DQ9
AW27
M_A_CS#0
13
SB_DQ9
M_B_DQ10
AY25
M_A_CS#1
13
SB_DQ10
M_B_DQ11
AW25
SB_DQ11
SA_ODT0
M_B_DQ12
AV27
SB_DQ12
M_B_DQ13
AU27
SB_DQ13
M_B_DQ14
AV25
M_A_RAS#
13
SB_DQ14
M_B_DQ15
AU25
M_A_WE#
13
SB_DQ15
M_B_DQ16
AM29
M_A_CAS#
13
SB_DQ16
M_B_DQ17
AK29
SB_DQ17
M_B_DQ18
AL28
M_A_BS0
13
SB_DQ18
M_B_DQ19
AK28
M_A_BS1
13
SB_DQ19
M_B_DQ20
AR29
M_A_BS2
13
SB_DQ20
M_B_DQ21
AN29
M_A_A[15:0]
13
SB_DQ21
M_A_A0
M_B_DQ22
AR28
SB_DQ22
M_A_A1
M_B_DQ23
AP28
SB_DQ23
M_A_A2
M_B_DQ24
AN26
SB_DQ24
M_A_A3
M_B_DQ25
AR26
SB_DQ25
M_A_A4
M_B_DQ26
AR25
SB_DQ26
M_A_A5
M_B_DQ27
AP25
SB_DQ27
M_A_A6
M_B_DQ28
AK26
SB_DQ28
M_A_A7
M_B_DQ29
AM26
SB_DQ29
M_A_A8
M_B_DQ30
AK25
SB_DQ30
M_A_A9
M_B_DQ31
AL25
SB_DQ31
M_A_A10
M_B_DQ32
AY23
SB_DQ32
M_A_A11
M_B_DQ33
AW23
SB_DQ33
M_A_A12
M_B_DQ34
AY21
SB_DQ34
M_A_A13
M_B_DQ35
AW21
SB_DQ35
M_A_A14
M_B_DQ36
AV23
SB_DQ36
M_A_A15
M_B_DQ37
AU23
SB_DQ37
M_B_DQ38
AV21
M_A_DQS#[7:0]
13
SB_DQ38
M_A_DQS#0
M_B_DQ39
AU21
SB_DQ39
M_A_DQS#1
M_B_DQ40
AY19
SB_DQ40
M_A_DQS#2
M_B_DQ41
AW19
SB_DQ41
M_A_DQS#3
M_B_DQ42
AY17
SB_DQ42
M_A_DQS#4
M_B_DQ43
AW17
SB_DQ43
M_A_DQS#5
M_B_DQ44
AV19
SB_DQ44
M_A_DQS#6
M_B_DQ45
AU19
SB_DQ45
M_A_DQS#7
M_B_DQ46
AV17
SB_DQ46
M_B_DQ47
AU17
M_A_DQS[7:0]
13
SB_DQ47
M_A_DQS0
M_B_DQ48
AR21
SB_DQ48
M_A_DQS1
M_B_DQ49
AR22
SB_DQ49
M_A_DQS2
M_B_DQ50
AL21
SB_DQ50
M_A_DQS3
M_B_DQ51
AM22
SB_DQ51
M_A_DQS4
M_B_DQ52
AN22
SB_DQ52
M_A_DQS5
M_B_DQ53
AP21
SB_DQ53
M_A_DQS6
M_B_DQ54
AK21
SB_DQ54
M_A_DQS7
M_B_DQ55
AK22
SB_DQ55
M_B_DQ56
AN20
SB_DQ56
M_B_DQ57
AR20
V_VREF_CA_DIMM
13,14
SB_DQ57
V_DDR_WR_VREF01
M_B_DQ58
AK18
SB_DQ58
V_DDR_WR_VREF02
M_B_DQ59
AL18
SB_DQ59
M_B_DQ60
AK20
SB_DQ60
M_B_DQ61
AM20
SB_DQ61
M_B_DQ62
AR18
SB_DQ62
M_B_DQ63
AP18
SB_DQ63
V_DDR_WR_VREF02
& TRACE
V_VCCDDQ
R306
R306
1.82K_1%_04
1.82K_1%_04
R305
R305
0_04
0_04
R307
R307
2.2_1%_06
2.2_1%_06
13
R301
R301
C285
C285
1.82K_1%_04
1.82K_1%_04
0.022u_16V_X7R_04
0.022u_16V_X7R_04
R300
R300
24.9_1%_04
24.9_1%_04
3
2
1
CHANNEL B
HSW_ULT_DDR3L
HSW_ULT_DDR3L
AM38
M_B_CLK_DDR#0
14
SB_CK#0
AN38
SB_CK0
M_B_CLK_DDR0
14
AK38
M_B_CLK_DDR#1
14
SB_CK#1
AL38
M_B_CLK_DDR1
14
SB_CK1
AY49
SB_CKE0
M_B_CKE0
14
AU50
SB_CKE1
M_B_CKE1
14
AW49
SB_CKE2
AV50
SB_CKE3
AM32
SB_CS#0
M_B_CS#0
14
AK32
SB_CS#1
M_B_CS#1
14
SB_ODT0
AL32
SB_ODT0
AM35
SB_RAS
M_B_RAS#
14
AK35
SB_WE
M_B_WE#
14
AM33
M_B_CAS#
14
SB_CAS
AL35
SB_BA0
M_B_BS0
14
AM36
SB_BA1
M_B_BS1
14
AU49
SB_BA2
M_B_BS2
14
M_B_A[15:0]
14
M_B_A0
AP40
SB_MA0
AR40
M_B_A1
SB_MA1
M_B_A2
AP42
SB_MA2
M_B_A3
AR42
SB_MA3
M_B_A4
AR45
SB_MA4
AP45
M_B_A5
SB_MA5
AW46
M_B_A6
SB_MA6
M_B_A7
AY46
SB_MA7
M_B_A8
AY47
SB_MA8
DDR CHANNEL B
DDR CHANNEL B
M_B_A9
AU46
SB_MA9
AK36
M_B_A10
SB_MA10
AV47
M_B_A11
SB_MA11
M_B_A12
AU47
SB_MA12
M_B_A13
AK33
SB_MA13
AR46
M_B_A14
SB_MA14
AP46
M_B_A15
SB_MA15
M_B_DQS#[7:0]
M_B_DQS#0
AW30
SB_DQSN0
AV26
M_B_DQS#1
SB_DQSN1
AN28
M_B_DQS#2
SB_DQSN2
M_B_DQS#3
AN25
SB_DQSN3
M_B_DQS#4
AW22
SB_DQSN4
M_B_DQS#5
AV18
SB_DQSN5
AN21
M_B_DQS#6
SB_DQSN6
AN18
M_B_DQS#7
SB_DQSN7
M_B_DQS[7:0]
14
M_B_DQS0
AV30
SB_DQSP0
AW26
M_B_DQS1
SB_DQSP1
AM28
M_B_DQS2
SB_DQSP2
M_B_DQS3
AM25
SB_DQSP3
M_B_DQS4
AV22
SB_DQSP4
M_B_DQS5
AW18
SB_DQSP5
AM21
M_B_DQS6
SB_DQSP6
M_B_DQS7
AM18
SB_DQSP7
4 OF 19
4 OF 19
MVREF_DQ_DIMMB
14
2,9,13,14,17,31
V_VCCDDQ
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[03] HASWELL ULT DDR CHANNEL-A/B
[03] HASWELL ULT DDR CHANNEL-A/B
[03] HASWELL ULT DDR CHANNEL-A/B
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
1.0
1.0
1.0
6-71-W3300-D03A
Date:
Date:
Date:
Friday, July 25, 2014
Friday, July 25, 2014
Friday, July 25, 2014
Sheet
Sheet
Sheet
3
3
3
of
of
of
41
41
41
2
1
D
C
14
B
A
Hide quick links:
Advertisement
Table of Contents
