Only For Training And Service Purposes - LG GU280 Service Manual

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User manual (154 pages)

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Table of Contents

3.6.2 Memory support (and LCD interface)

The QSC62x0 device has two external bus interface (EBI) ports: EBI1 and EBI2.

EBI1 supports high-speed synchronous dynamic devices. Its memory controller supports the new

mobile DDR SDRAM memories with its higher bandwidth and ability to run at high clock

frequencies. This interface supports the high-bandwidth, high-density, and low-latency

requirements of the QSC's advanced on-chip capabilities such as the ARM9 processor, highperformance

graphics, and video applications.

EBI2 is the slower speed interface intended to support memory devices such as NAND flash and

asynchronous SRAM, peripheral devices such as LCDs, and the UBM receiver for multicast or

broadcast reception (QSC6270 only). In addition, EBI2 is required to support a synchronous-burst

AAD NOR flash to enable a NOR/DDR SDRAM memory configuration because the simultaneous

mode (NOR, SDRAM) is not supported on the EBI1 bus.

The ARM926EJ-S microprocessor is a cached processor and all its accesses to external memory

use burst techniques of four or eight 32-bit words when the memory region is declared to be

cacheable/bufferable. To take advantage of this QSC higher performance feature, data from

memories must satisfy the requirements for these burst accesses.

DDR

SDRAM

DDR

512Mbit

SDRAM

512Mbit

External Memory (MICRO-

SD card)