LG GU280 Service Manual page 110

7. CIRCUIT DIAGRAM
16 15
L
UART_TP
TP301
UART_BT_SEL
Connect to GND on PCB Array
USB_DP
USB_DM
VBUS
VBATT
TP303
KPDPWR_N
VBUS
TP305
UART1_TX_DATA
TP304
K UART1_RX_DATA
J
I
High : BT UART
Low : UART Comm
UART_BT_SEL
H
BT_PWR_ON
LCD_MAKER_ID
VREG_MSMP_2.6V
CAM_LDO_EN
GSM_SW_MODE
I2C_SDA_BL
I2C_SCL_BL
SLIDE_DETECT
LCD_BACKLIGHT_CONT
TRK_LO_ADJ
PA_R0
G
PA_R1
ANT_SEL[0]
ANT_SEL[1]
ANT_SEL[2]
ANT_SEL[3]
LCD_RST
VGA_CAM_PWDN
F VGA_CAM_RST
NAND_READY
USIM_DATA
USIM_CLK
USIM_RST
USW_INT
LCD_IF[2]
I2C2_SCL
I2C2_SDA
I2C_SCL
I2C_SDA
CAMIF_MCLK
E
CAMIF_DATA[7]
CAMIF_DATA[6]
CAMIF_DATA[5]
CAMIF_DATA[4]
CAMIF_DATA[3]
CAMIF_DATA[2]
CAMIF_DATA[1]
CAMIF_DATA[0]
CAM_PWDN
LCD_IF[1]
CAM_RST
CAMIF_VSYNC
CAMIF_HSYNC
D CAMIF_PCLK
LCD_VSYNC
BT_PCM_CLK
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_SYNC
KEY_ROW[0]
KEY_ROW[1]
KEY_ROW[2]
KEY_ROW[3]
KEY_ROW[4]
KEY_COL[0]
KEY_COL[1]
C KEY_COL[2]
KEY_COL[3]
KEY_COL[4]
UART1_RFR_N
UART1_CTS_N
MICROSD_CLK
MICROSD_DATA[3]
MICROSD_DATA[2]
MICROSD_DATA[1]
MICROSD_DATA[0]
MICROSD_CMD
MICROSD_DETECT
B
A
16 15
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
14 13 12 11 10
JTAG
CTS
12
RTS
TP 11
DSR
10 CN301
NC4 UTXD
9
G1 G2
NC3 URXD
8
NC2 PWR 1 10
7 JTAG_TCK
VBAT
VBAT 2 9
6 JTAG_TDI JTAG_TMS
ON_SW ON_SW 3 8
5 PS_HOLD JTAG_TRST_N
NC1 VCHAR 4 7
TP MSM_RESIN_N JTAG_TDO
4
TX TX 5 6
3 JTAG_RTCK
RX RX
TP 2
GND GND G3 G4
TP 1
AXT610124
2.5G 3G
UART1
C301
2p
AC3
GPIO_77
AB1
GPIO_76
AB2
GPIO_75
TP302 AA3
GPIO_74
AB8
GPIO_73
TP AA7
GPIO_72
V8
GPIO_71
W9
GPIO_70
W8
GPIO_69
W7
GPIO_68
W6
GPIO_67
V7
GPIO_66
T14
GPIO_65
C17
GPIO_64
C16
GPIO_63
A16
GPIO_62
B16
GPIO_61
A17
GPIO_60
B17
GPIO_59
E15
GPIO_58
B15
C309 GPIO_57
A14
DNI GPIO_56
F14
GPIO_55
A13
GPIO_54
E8
GPIO_53
F8
GPIO_52
F7
GPIO_51
E7
GPIO_50
A7
GPIO_49
B7 U201
GPIO_48
AC5
GPIO_47
AB6
GPIO_46
AC4
GPIO_45
QSC6240_DATA,QSC6240_POWER
H10
GPIO_44
C9
GPIO_43
B9
GPIO_42
H12
GPIO_41
B10
GPIO_40
A10
GPIO_39
A11
GPIO_38
C14
GPIO_37
B14
GPIO_36
F13
GPIO_35
B13
GPIO_34
C13
GPIO_33
F12
GPIO_32
B12
GPIO_31
C12
GPIO_30
E13
GPIO_29
B11
GPIO_28
E12
GPIO_27
E11
GPIO_26
C11
GPIO_25
E14
GPIO_24
G6
GPIO_23
C8
GPIO_22
E9
GPIO_21
B8
GPIO_20
A8
GPIO_19
W1
GPIO_18
V1
GPIO_17
V2
GPIO_16
W2
GPIO_15
W3
GPIO_14
Y1
GPIO_13
Y2
GPIO_12
AA1
GPIO_11
Y3
GPIO_10
AA2
GPIO_9
F11
GPIO_8
F10
GPIO_7
AB4
GPIO_6
AA6
GPIO_5
AB5
GPIO_4
AA5
GPIO_3
AA4
GPIO_2
AB3
GPIO_1
C15
GPIO_0
GND
14 13 12 11 10
9 8 7 6 5
MODE
MODE_3 MODE_2 MODE_1 MODE_0
0 0 0 1
* MODE_3 : Not connected(internally pulled-down) - Enabled by HW
C303
100n
SDRAM_ADDR[0:15]
K6 SDRAM_ADDR[15]
EBI1_A_D_31
SDRAM_ADDR[14]
M6
EBI1_A_D_30
SDRAM_ADDR[13]
M5
EBI1_A_D_29
SDRAM_ADDR[12]
N5
EBI1_A_D_28
K3 SDRAM_ADDR[11]
EBI1_A_D_27 SDRAM_ADDR[10]
M3
EBI1_A_D_26
SDRAM_ADDR[9]
L6
EBI1_A_D_25
SDRAM_ADDR[8]
H3
EBI1_A_D_24
N6 SDRAM_ADDR[7]
EBI1_A_D_23 SDRAM_ADDR[6]
R5
EBI1_A_D_22 SDRAM_ADDR[5]
P6
EBI1_A_D_21
SDRAM_ADDR[4]
T5
EBI1_A_D_20
SDRAM_ADDR[3]
P3
EBI1_A_D_19
T6 SDRAM_ADDR[2]
EBI1_A_D_18
T3 SDRAM_ADDR[1]
EBI1_A_D_17 SDRAM_ADDR[0]
U3
EBI1_A_D_16
SDRAM_DATA[15]
G2
EBI1_A_D_15 SDRAM_DATA[0:15]
G1 SDRAM_DATA[14]
EBI1_A_D_14
H1 SDRAM_DATA[13]
EBI1_A_D_13 SDRAM_DATA[12]
H2
EBI1_A_D_12
SDRAM_DATA[11]
K1
EBI1_A_D_11
SDRAM_DATA[10]
K2
EBI1_A_D_10
SDRAM_DATA[9]
L1
EBI1_A_D_9
L2 SDRAM_DATA[8]
EBI1_A_D_8 SDRAM_DATA[7]
M1
EBI1_A_D_7
SDRAM_DATA[6]
M2
EBI1_A_D_6
SDRAM_DATA[5]
N1
EBI1_A_D_5
SDRAM_DATA[4]
N2
EBI1_A_D_4
R1 SDRAM_DATA[3]
EBI1_A_D_3
R2 SDRAM_DATA[2]
EBI1_A_D_2 SDRAM_DATA[1]
T1
EBI1_A_D_1
SDRAM_DATA[0]
T2
EBI1_A_D_0
A5 EBI2_DATA[15]
EBI2_A_D_15 EBI2_DATA[0:15]
B5 EBI2_DATA[14]
EBI2_A_D_14 EBI2_DATA[13]
C5
EBI2_A_D_13
EBI2_DATA[12]
A4
EBI2_A_D_12
EBI2_DATA[11]
C4
EBI2_A_D_11
EBI2_DATA[10]
A3
EBI2_A_D_10
B4 EBI2_DATA[9]
EBI2_A_D_9 EBI2_DATA[8]
D3
EBI2_A_D_8
EBI2_DATA[7]
E3
EBI2_A_D_7
EBI2_DATA[6]
B3
EBI2_A_D_6
EBI2_DATA[5]
C2
EBI2_A_D_5
B1 EBI2_DATA[4]
EBI2_A_D_4 EBI2_DATA[3]
C1
EBI2_A_D_3 EBI2_DATA[2]
D2
EBI2_A_D_2
EBI2_DATA[1]
D1
EBI2_A_D_1
EBI2_DATA[0]
E1
EBI2_A_D_0
P1
EBI1_DQS_0 SDRAM_DQS[0]
J1
EBI1_DQS_1 SDRAM_DQS[1]
P2
EBI1_DQM_0 SDRAM_DQM[0]
J2
EIB1_DQM_1 SDRAM_DQM[1]
F3
EBI1_CKE_0
SDRAM_CKE[0]
P5
EBI1_CKE_1
H6
EBI1_CS0_N SDRAM_CS_N[0]
J5
EBI1_CS1_N
J6
EBI1_ADV_N
SDRAM_ADV_N
G5
EBI1_OE_N SDRAM_OE_N
H5
EBI1_WE_N SDRAM_WE_N
K5 R305 18
EBI1_M_CLK SDRAM_CLK_P
L5 R306 18
EBI1_M_CLK_N SDRAM_CLK_M
B6
LCD_RS LCD_ADS
F5
LCD_EN
C7
LCD_CS_N LCD_CS_N
E6
EBI2_WE_N EBI2_WE_N
F2
EBI2_OE_N EBI2_OE_N
F1
EBI2_UB_N EBI2_CLE_N
C6
EBI2_LB_N EBI2_ALE_N
E5
EBI2_CS1_N EBI2_CS1_N
E2
EBI2_CS0_N
A2
EBI2_M_CLK
9 8 7 6 5
- 111 -
4 3 2 1
L
ADC HKAIN1:PCB_Rev_ADC
( Default Pull-Down)
100K : 6.2K : 0.128V - A, G
HKAIN0 - VBATT_TEMP K
Native ARM9 JTAG
HKAIN1 - PCB_Rev_ADC 100K : 13K : 0.253V - B, H
MPP1 - VREF_RFA_2.2V (internally) 100K : 22K : 0.396V - C, I
MPP2 - Null
100K : 47K : 0.703V - D, J
MPP3 - KYBD_BACKLIGHT
100K : 62K : 0.842V - F, L
MPP4 - Null
LCD_DRV_N - SUB_BACKLIGHT 100K : 91K : 1.048V - 1.0
100K : 150K : 1.32V - 1.1
100K : 240K : 1.553V - 1.2
100K : 470K : 1.814V - 1.3
100K : 1.5M : 2.062V - 1.4
J
I
H
G
F
E
D
C
B
A
4 3 2 1
LGE Internal Use Only