Only For Training And Service Purposes - LG GU280 Service Manual

3. Technical Brief
Shared UMTS/GSM configuration (four GSM LNAs)
In this configuration, the GSM 850 receive path shares the UMTS 850 receiver front-end path (including LNA).
Beginning at the antenna switch output, the GSM signal is routed through the UMTS850 duplexer to the shared LNA
input at pins L22 and K22. Likewise, the GSM 1900 receive path shares the UMTS 1900 front-end, including pins J23 and
H23. The GSM 900 and GSM 1800 bands have dedicated receive paths from the antenna switch outputs to the QSC LNA
inputs. Each band has its own band-select filter that drives its LNA input. All four GSM bands include input filtering:
the 850 and 1900 bands share the UMTS duplexer filtering, while the 900 and 1800 bands have dedicated bandpass
filters. The filter functions suppress out-of-band received signals and the handset's GSM transmitter leakage.
Transmit power suppression must be adequate to avoid overdriving the GSM Rx chain. Like the UMTS paths,
the GSM paths use a differential configuration into their LNAs, and thus equire differential matching networks.
The internal GSM receivers are functionally identical to the UMTS receivers: although there are multiple GSM LNAs,
only one is active at a time. The active gain-stepped LNA output drives a shared quadrature downconverter directly
— an off-chip inter-stage filter is not required. The elimination of this filter is achieved by a combination of factors:
New on-chip QSC processing
Higher performance achieved by the differential duplexer-to-LNA interface
Greater duplexer suppression of Tx leakage
The downconverter's RF circuitry includes another gain-stepped amplifier that supplements the LNA gain steps
to further extend the receiver dynamic range. The downconverter translates the active LNA's RF signal directly to
baseband,
producing two analog outputs: in-phase (I) and quadrature (Q). The GSM baseband signals drive lowpass filters whose
passband and stopband characteristics are optimized for the active GSM waveform. Both filter outputs are buffered
to drive their analog-to-digital converters for digitization. The digital baseband outputs are routed to QSC baseband
circuits for further processing. The Rx LO signal is delivered to the downconverter circuits from the LO generation and
distribution circuits as described in next section.
Dedicated GSM configuration (two GSM LNAs)
In this configuration, the GSM 850 and GSM 1900 bands do not pass through the UMTS duplexers.
Instead, the two GSM LNA inputs are shared: the GSM 850 and GSM 900 bands share the low-band GSM LNA,
and the GSM 1800 and GSM 1900 bands share the high-band LNA. Four switch module outputs are required, each
driving its own GSM Rx path. A two-way SAW filter takes the two low-band (or high-band) single-ended inputs from the
antenna switch and provides one filtered, differential output that drives the appropriate QSC LNA input.
Beyond the LNA inputs, this GSM receiver configuration is identical to the paths described earlier for the shared
UMTS/GSM configuration.
3.3.3. Rx LO circuits
The QSC62x0 device integrates all of the frequency synthesizer functions that generate the UMTS and GSM receive
LO signals (UHF local oscillator, PLL circuits, and loop filter), plus the distribution circuits that deliver the quadrature
LO signals to the two downconverters. The buffered 19.2 MHz TCXO or XO signal provides the synthesizer input (REF),
the frequency reference to which the PLL is phase and frequency locked. The reference is divided to create a fixed
frequency input to the phase detector, FR. The other phase detector input (FV) varies as the loop acquires a lock and is
generated by dividing the local oscillator output frequency using the feedback path's counter. The closed-loop will
force FV to equal FR when locked. If the loop is not locked, the error between FV and FR will create an error signal. This
error signal is filtered by the loop filter and applied to the local oscillator, tuning the output frequency so that the error
is decreased. Ultimately the loop forces the error to approach zero and the PLL is phase and frequency locked.
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Only for training and service purposes