Yamaha RX-V1067 Service Manual page 97

A B
1
Y
Pb/Cb
MONITOR OUT
/ZONE OUT
Pr/Cr
2
Y
Pb/Cb
Y,Pb,Pr
AV1
3
Pr/Cr
Pb/Cb
AV2
Pr/Cr
V
Y
Pb/Cb
AV3
Pr/Cr
Y
4
Pb/Cb
AV4
Pr/Cr
V
AV1
C Y
INPUT
Y
SELECTOR
V
IC301
AV2
C
C
Y INPUT
SELECTOR
V
IC302
AV3
5 C
Y
V
AV4
C
Y
ZONE
Y
SELECTOR
IC303
V
V-AUX
C
C
ZONE
Y
SELECTOR
IC304
V
Y
DOCK
C
6
V
Drv
AV OUT
Drv
C
Drv
Y
Tr
V
MONITOR OUT
/ZONE OUT
7
Y
C
C D
HDMI/VIDEO Section Block Diagram
HDMI(VID)_SCL
HDMI(VID)_SDA
YOUT1
PBOUT1
YPbPr3-6 PBOUT1
6dB Drv
YOUT2
DAY, DAPb, DAPr PBOUT2
ADY, ADPb, ADPr
YPbPr2 PBOUT2
6dB Drv
iPod
PROUT4
Y, C
ADLuma, ADC
Pr1, Y1 YOUT4
0/6 Buf
iPod Pb1
PROUT3
AVLuma, AVC
YOUT3
0/6 Buf
ADCVBS
V1-6 VOUT4
0/6 Buf
AVCVBS
VOUT5
0/6 Buf
MONC
DACVBS VOUT1
V7 6dB Drv
Y MONCVBS
V8 VOUT2
6dB Drv
C
MONLuma
V9 VOUT3
6dB Drv
VIDEO SELECTOR
IC305
Y
4051
C
4051
INLuma Y
OUTLuma
Z2Luma OUTPUT
DALuma SELECTOR
IC308
INC
C
Z2C OUTC
OUTPUT
Y
DAC
SELECTOR
4052
4051
C
4051
→
VIDEO (1)
SCHEMATIC DIAGRAM
E F G
HDMI IN
IN7 IN6 IN5 IN4
1
2
IC2
0
HDMI SW.
SiI9185A
INT
LSDA
R
LSCL
HEQ_N_RST HEQ_SDA
HEQ_SCL
3
2 1
IC3
HRX_27MHz XTALIN
HDMI
DUAL RECEIVER
HDMI_SDA
CSCL
HDMI_SCL CSDA
Sil9233A
HRX_N_RST
RESET
HRX_N_INT ODCK
INT
HSYNC
VSYNC
Q[35-24]Q[23-12] Q[11-0]
DE
12 12 12 4
480i ~ 1080i
480i ~ 1080i
10 10 4
XL31 HRX_VSEL
XTAL
28.63636MHz
4
10 10
SOY IC32
Circuit only
ADY
AIN1
10 Video signal no pass
A/D
P[29-20]
ADPb
VIDEO DECODER
AIN2 10
P[19-10]
ADPr
AIN3
AT
ADV7800-80 P[9-2]
ADC T
AIN12 LLC
3
4
HS-OUT
ADCVBS
VS-OUT
AIN11
FLD-DE
ADLuma
AIN10
SFL
SDA
/RESET SCLK /INT
DV_SCL
VDEC_N_RST VDEC_N_INT
DV_SDA
DACVBS DAV
SCRESET/RTC
DAC 4
IC41
DAC
DAC
DAC 5 480i/576i
VIDEO ENCODER
DALuma S[7-0]
DAC 6
D/A
DAY DAY
DAC 1 CLKIN
/HSYNC
DAPb ADV7172
DAPb /VSYNC
DAC 2
DAPr
DAPr
DAC 3
DV_SCL
SCL
DV_SDA
SDA
/RESET
VDEC_N_RST
H I
DIGITAL (2)
HDMI SCHEMATIC DIAGRAM
FRONT IN
CEC
HDMI OUT
IC94
HDMI EQ
TMDS141
CE
IN3 IN2 IN1 OUT2
CEC
ARC
F_HEQ_CE
1
+5VPower
IC1 CEC_RY1
Power IC
2 HDMI SW. 0 CEC_RY2
SiI9185A
INT
LSDA
RESET# HMCK
LSCL
HBCK_DCLK
HWCK_DSDR0
HPSD0_DSDL0
HEQ_N_RST HEQ_SDA HDMI_SCL
HPSD1_DSDR1
DIGITAL
HPSD2_DSDl1
HTX2_N_RST HDMI_SDA
HEQ_SCL
HPSD3_DSDL2
HDIG_DSDL2 DSP Block
0
8 GPIO
RESET CSCL
AUP_SD0 MCLK
CSDA
SCK
AUP_WCK 4 IC71
MCLK
AUP_BCK WS
SCK
SD0
AUP_MCK
WS HDMI
SD0 S_SD0
HDMI_AUDIO
S_WS 4 TRANSMITTER
SD1
4
SD2 S_SCK
8
S_MCLK
SD3
SPDIF Sil9134
4
SD1
IDCK
MUTEOUT SD2
GPIO3
VSYNC
SD3
HD_LED HSYNC
GPIO5 SPDIF
D[35-24] D[23-12] D[11-0]
DE
12 12 12 4
12 12 12 4
12
12
12
4
XL61
27MHz
IC64
+3.3DV
VIDEO PROCESSOR
8
3
FPGA
8
Data:8bit
DIGITAL (1)
SCHEMATIC DIAGRAM
J
RX-V1067/HTR-8063/RX-A1000
→
OUT1
+5VPower
Power IC
HDMI_PON
HDMI_SCL
HTX1_N_RST HDMI_SDA
GPIO
RESET CSCL
CSDA
MCLK IC75
SCK
WS
HDMI
SD0
TRANSMITTER
Sil9134
SD1 IDCK
SD2
VSYNC
SD3 HSYNC
SPDIF D[35-24] D[23-12] D[11-0]
DE
12 12 12 4
IC62
128Mbit
SDRAM
480i ~ 1080i 99MHz
16bit
→
97