Yamaha RX-V1067 Service Manual page 82

RX-V1067/HTR-8063/RX-A1000
Pin Use
Port Name
No. Port
D17/CLK6/
89 CLK6 FPGA_SCL
P12_1
D16/TXD6/
90 SDA6/SRXD6/ TXD6
P12_0
91 VCC VCC
A8/[A8/D8]/
92 TA0OUT/UD0A/ A8
UD1A/P3_0
93 VSS VSS
A7/[A7/D7]/
94 A7
AN2_7/P2_7
A6/[A6/D6]/
95 A6
AN2_6/P2_6
A5/[A5/D5]/
96 A5
AN2_5/P2_5
A4/[A4/D4]/
97 A4
AN2_4/P2_4
A3/[A3/D3]/
98 A3
AN2_3/P2_3
A2/[A2/D2]/
99 A2
AN2_2/P2_2
A1/[A1/D1]/BC2/
100 [BC2/D1]/AN2_1/ A1
P2_1
A0/[A0/D0]/BC0/
101 [BC0/D0]/AN2_0/ A0
P2_0
D15/INT5/
102 IIO0_7/IIO1_7/ D15
P1_7
D14/INT4/
103 IIO0_6/IIO1_6/ D14
P1_6
D13/INT3/
104 IIO0_5/IIO1_5/ D13
P1_5
D12/IIO0_4/
105 D12
IIO1_4/P1_4
D11/IIO0_3/
106 D11
IIO1_3/P1_3
D10/IIO0_2/
107 D10
IIO1_2/P1_2
D9/IIO0_1/
108 D9
IIO1_1/P1_1
IIO0_0/IIO1_0/
109 D8
D8/P1_0
110 AN0_7/D7/P0_7 D7
111 AN0_6/D6/P0_6 D6
112 AN0_5/D5/P0_5 D5
113 AN0_4/D4/P0_4 D4
114 WR3/BC3/P11_4 P11_4 EEP_N_CS
IIO1_3/RTS8/
115 CTS8/WR2/CS3/ CS3
P11_3
IIO1_2/RXD8/
116 RXD8 EEP_MISO
CS2/P11_2
IIO1_1/CLK8/
117 CLK8 EX_CLK
CS1/P11_1
IIO1_0/TXD8/
118 TXD8 EX_MOSI
CS0/P11_0
119 AN0_3/D3/P0_3 D3
120 AN0_2/D2/P0_2 D2
121 AN0_1/D1/P0_1 D1
82
Related Power Supply
Function Terminal
Name Processing
HDMI_PON O
FPGA_
HDMI_PON O
MOSI
VCC
A[8] HDMI_PON O
VSS
A[7] HDMI_PON O
A[6] HDMI_PON O
A[5] HDMI_PON O
A[4] HDMI_PON O
A[3] HDMI_PON O
A[2] HDMI_PON O
A[1] HDMI_PON O
A[0] HDMI_PON O
D[15] 100kPD HDMI_PON
D[14] 100kPD HDMI_PON
D[13] 100kPD HDMI_PON
D[12] 100kPD HDMI_PON
D[11] 100kPD HDMI_PON
D[10] 100kPD HDMI_PON
D[9] 100kPD HDMI_PON
D[8] 100kPD HDMI_PON
D[7] 100kPD HDMI_PON
D[6] 100kPD HDMI_PON
D[5] 100kPD HDMI_PON
D[4] 100kPD HDMI_PON
10kPU AC
FPGA_N_
HDMI_PON O
CS
AC
FL/expansion,
suction AC
prevention
FL/expansion,
suction AC
prevention
D[3] 100kPD HDMI_PON
D[2] 100kPD HDMI_PON
D[1] 100kPD HDMI_PON
OFF ON
I/O Logic I/O Logic
Low O Clk FPGA clock (at Boot)
Low O Data FPGA transmission data (at Boot)
---
Low B Bus External bus
---
Low B Bus External bus
Low B Bus External bus
Low B Bus External bus
Low B Bus External bus
Low B Bus External bus
Low B Bus External bus
Low B Bus External bus
Low B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
O Low O L act EEPROM chip select
Low B Bus External bus
O Low I Data FL/Expansion IO/EEPROM reception data
O Low O Clk FL/Expansion IO/EEPROM communication clock
O Low O Data FL/Expansion IO/EEPROM transmission data
I --- B Bus External bus
I --- B Bus External bus
I --- B Bus External bus
Detail of Function