QQ
3 7 63 1515 0
Pin No.
Pin Name
91
92
OVDDE2
93 to 95
QR7 to QR9
96
97
98
99
100
101
102
103
OVDDE3
104
105
106
107
108
109
110
111
112
113
TE
114
L 13942296513
115
116
OVDDE4
117
118
119
120
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I/O
VSS
—
Digital ground
—
Digital positive supply voltage (+3.3V) for Pad Ring
O
R data output
QV
O
Vertical sync output
QH
O
Horizontal sync output
QDE
O
Data enable output
QCLK
O
Pixel clock output
VDDI
—
Digital positive supply voltage (+2.5V) for Pad Ring
VSS
—
Digital ground
EXCLK
I
Pixel clock input for external PLL mode (must be connected to ground)
—
Digital positive supply voltage (+3.3V) for Pad Ring
PH1
O
Phase comparate signal-1 for external PLL (not used)
N.C
—
Not used
AVS1
—
Analog ground for PLL (must be connected to ground)
AVD1
—
Digital positive supply voltage (+3.3V) for PLL
CPO
O
Charge pump output for internal PLL
N.C
—
Not used
VCI
I
VCO input for internal PLL
AVS2
—
Analog ground for PLL
AVD2
—
Digital positive supply voltage (+3.3V) for PLL
N.C
—
Not used
PH2
O
Phase comparate signal-2 for external PLL (not used)
PLLEN
I
PLL mode select signal input (internal mode or external mode)
—
Digital positive supply voltage (+3.3V) for Pad Ring
DCLK
I
System clock input (27MHz)
OVSS1
—
Digital ground
DCLKP
I
DCLK polarity control signal input (must be connected to ground)
VDDI
—
Digital positive supply voltage (+2.5V) for Pad Ring
x
ao
y
i
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
HCD-FX999W/FX1000W
2 9
9 4
2 8
Desciption
1 5
0 5
8
2 9
9 4
m
co
Ver. 1.1
9 9
2 8
9 9
91