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7.3 Registers Controlling Watchdog Timer
The following two registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL2 to 00H.
Symbol
7
6
5
TCL2
0
0
0
TCL22
TCL21
TCL20
0
0
0
0
1
0
1
0
0
1
1
0
Other than above
Remarks 1. f
: System clock oscillation frequency
X
2. The parenthesized values apply to operation at f
CHAPTER 7
WATCHDOG TIMER
Figure 7-2. Format of Timer Clock Select Register 2
4
3
2
1
0
0
TCL22 TCL21 TCL20
Watchdog timer count clock selection
4
f
/2
(375 kHz)
X
6
f
/2
(93.8 kHz)
X
8
f
/2
(23.4 kHz)
X
10
f
/2
(5.86 kHz)
X
Settings prohibited
User's Manual U12978EJ3V0UD
0
Address
After reset
FF42H
00H
µ
(341 s)
2
11
/f
X
2
13
/f
(1.37 ms)
X
2
15
/f
(5.46 ms)
X
2
17
/f
(21.8 ms)
X
= 6.0 MHz.
X
R/W
R/W
Interval time
93
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