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NEC switch User Manual

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User's Manual
µ µ µ µ PD789800 Subseries
8-Bit Single-Chip Microcontrollers
µ µ µ µ PD789800
µ µ µ µ PD78F9801
Document No. U12978EJ3V0UD00 (3rd edition)
Date Published February 2003 N CP (K)
Printed in Japan
1998, 2003

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   Summary of Contents for NEC switch

  • Page 1

    User’s Manual µ µ µ µ PD789800 Subseries 8-Bit Single-Chip Microcontrollers µ µ µ µ PD789800 µ µ µ µ PD78F9801 Document No. U12978EJ3V0UD00 (3rd edition) Date Published February 2003 N CP (K) 1998, 2003 Printed in Japan...

  • Page 2

    [MEMO] User’s Manual U12978EJ3V0UD...

  • Page 3

    Reset operation must be executed immediately after power-on for devices having reset function. FIP and EEPROM are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

  • Page 4

    NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

  • Page 5

    Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...

  • Page 6

    Page Throughout Deletion of CU-type and GB-3BS type packages Deletion of indication “under development” for µ PD78F9801 p. 21 Modification of operating ambient temperature when flash memory is written in 1.1 Features p. 27 Addition of outline of timer in 1.7 Functions pp.

  • Page 7

    Readers This manual is intended for users who wish to understand the functions of the µ PD789800 Subseries and who design and develop its application systems and programs. Target products: • µ PD789800 Subseries: µ PD789800 and µ PD78F9801 Purpose This manual is intended to give users an understanding of the functions described in the Organization below.

  • Page 8

    Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD789800 Subseries User’s Manual 78K/0S Series Instructions User’s Manual Documents Related to Development Tools (Software) (User’s Manuals) RA78K0S Assembler Package CC78K0S C Compiler SM78K Series System Simulator Ver.

  • Page 9

    Other Related Documents SEMICONDUCTOR SELECTION GUIDE - Products and Packages - (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Caution The related documents listed above are subject to change without notice.

  • Page 10: Table Of Contents

    CHAPTER 1 GENERAL... 21 Features ... 21 Applications... 21 Ordering Information ... 21 Pin Configuration (Top View)... 22 78K/0S Series Lineup... 23 Block Diagram ... 26 Functions ... 27 CHAPTER 2 PIN FUNCTIONS ... 28 List of Pin Functions... 28 Pin Functions ...

  • Page 11

    3.3.4 Register addressing ...50 Operand Address Addressing...51 3.4.1 Direct addressing ...51 3.4.2 Short direct addressing ...52 3.4.3 Special function register (SFR) addressing...53 3.4.4 Register addressing ...54 3.4.5 Register indirect addressing...55 3.4.6 Based addressing ...56 3.4.7 Stack addressing...56 CHAPTER 4 PORT FUNCTIONS...57 Port Functions ...57 Port Configuration...59 4.2.1...

  • Page 12

    CHAPTER 7 WATCHDOG TIMER ... 91 Watchdog Timer Functions... 91 Watchdog Timer Configuration ... 92 Registers Controlling Watchdog Timer ... 93 Watchdog Timer Operation ... 95 7.4.1 Operation as watchdog timer... 95 7.4.2 Operation as interval timer... 96 CHAPTER 8 USB FUNCTION ...

  • Page 13

    11.4.2 Maskable interrupt acknowledgment operation...173 11.4.3 Multiplexed interrupt servicing...175 11.4.4 Interrupt request hold ...177 CHAPTER 12 STANDBY FUNCTION...178 12.1 Standby Function and Configuration ...178 12.1.1 Standby function ...178 12.1.2 Register controlling standby function ...179 12.2 Standby Function Operation ...180 12.2.1 HALT mode ...180 12.2.2 STOP mode...183...

  • Page 14

    Register Index (Alphabetic Order of Register Name) ... 229 Register Index (Alphabetic Order of Register Symbol)... 231 APPENDIX C REVISION HISTORY ... 233 User’s Manual U12978EJ3V0UD...

  • Page 15

    Figure No. Pin I/O Circuits ... 34 Memory Map ( µ PD789800) ... 35 Memory Map ( µ PD78F9801)... 36 Data Memory Addressing ( µ PD789800) ... 38 Data Memory Addressing ( µ PD78F9801) ... 39 Configuration of Program Counter ... 40 Configuration of Program Status Word ...

  • Page 16

    Figure No. Interval Timer Operation Timing of 8-Bit Timer/Event Counter 01... 86 Timing of External Event Counter Operation (with Rising Edge Specified) ... 87 Timing of Square-Wave Output ... 89 6-10 Start Timing of 8-Bit Timer Counter ... 90 6-11 Timing of External Event Counter Operation ...

  • Page 17

    Figure No. 8-31 Flow Chart of NRZI Encoder Operation ... 150 8-32 Timing of Bit Stuffing/Strip Controller Operation ... 151 8-33 Flow Chart of Bit Stuffing Control Operation ... 152 8-34 Flow Chart of Bit Strip Control Operation ... 153 Block Diagram of Serial Interface 10...

  • Page 18

    Figure No. 14-3 Example of Connection with Dedicated Flash Programmer ... 193 14-4 Pin Connection Example... 195 14-5 Signal Conflict (Input Pin of Serial Interface)... 196 14-6 Abnormal Operation of Other Device... 196 14-7 Signal Conflict (RESET Pin) ... 197 14-8 Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O...

  • Page 19

    Table No. Type of Pin I/O Circuit Recommended Connection of Unused Pins ... 33 Vector Table... 37 Special Function Register List... 45 Functions of Ports ... 58 Configuration of Port ... 59 Port Mode Register and Output Latch Settings When Using Alternate Functions ... 70 Configuration of Clock Generator...

  • Page 20

    Table No. 12-3 STOP Mode Operation Status ... 183 12-4 Operation After Release of STOP Mode ... 185 13-1 Hardware Status After Reset ... 188 Differences Between µ PD78F9801 and Mask ROM Versions ... 190 14-1 14-2 Communication Mode List ... 192 14-3 Pin Connection List...

  • Page 21: Chapter 1 General

    1.1 Features • On-chip USB functions • Implements a USB (Universal Serial Bus) by connecting to Hub and Host. • Transfer speed: 1.5 Mbps (at 6.0 MHz operation with system clock) • On-chip regulator • Controls the USB port voltage by using a bus power supply (V driver/receiver.

  • Page 22: Pin Configuration (top View)

    1.4 Pin Configuration (Top View) • 44-pin plastic LQFP (10 × 10) µ PD789800GB-×××-8ES, µ PD78F9801GB-8ES Cautions 1. Connect the IC pin directly to the V 2. Directly connect the V Remark The parenthesized values apply to the µ PD78F9801. Internally connected INTP0: Interrupt from peripherals...

  • Page 23: 0s Series Lineup

    1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Small-scale package, general-purpose applications µ 44-pin PD789046 µ 42-/44-pin PD789026 µ 30-pin PD789088 µ 30-pin PD789074 µ 28-pin PD789014 µ...

  • Page 24

    The major differences between subseries are shown below. Series for General-Purpose and LCD Drive Function Capacity Subseries 8-Bit 16-Bit Watch WDT (Bytes) µ PD789046 Small- 16 K 1 ch scale µ PD789026 4 K to 16 K package, µ PD789088 16 K to 32 K 3 ch general- µ...

  • Page 25

    Series for ASSP Function Capacity Subseries 8-Bit 16-Bit Watch WDT (Bytes) µ PD789800 2 ch µ PD789842 Inverter 8 K to 16 K 3 ch Note 1 1 ch control µ PD789850 On-chip 16 K 1 ch controller µ PD789861 Keyless 2 ch entry...

  • Page 26: Block Diagram

    1.6 Block Diagram KR00 to KR07 Key return 0 8-bit timer 00 8-bit timer/event TI01/TO01/P26/INTP0 counter 01 Watchdog timer REGC Regulator USBDM function 0 USBDP SCK10/P20 Serial SO10/P21 interface 1 SI10/P22 Interrupt INTP0/P26 control Remark The parenthesized values apply to the µ PD78F9801. CHAPTER 1 GENERAL 78K/0S...

  • Page 27: Functions

    1.7 Functions Product Item Internal memory High-speed RAM Minimum instruction execution time Instruction set I/O ports Serial interface Timer Regulator Vector interrupt Maskable sources Non-maskable Power supply voltage Operating ambient temperature Package An outline of the timer is shown below. Operation mode Interval timer External event counter...

  • Page 28: Chapter 2 Pin Functions

    2.1 List of Pin Functions (1) Port pins Pin Name P00 to P07 Port 0 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of on-chip pull-up resistors can be specified by pull-up resistor option register 0 (PU0). When used as an output port, CMOS output or N-ch open-drain output can be specified in 8-bit units by port output mode register 0 (POM0).

  • Page 29

    (2) Non-port pins Pin Name INTP0 Input External interrupt request input for which valid edge (rising and/or falling edge) can be specified KR00 to Input Input for detecting key return signals KR07 — No connection. Can be left open. REGC —...

  • Page 30: Pin Functions

    2.2 Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit I/O port and can be set to the input or output port mode in 1-bit units by using port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used by setting pull-up resistor option register 0 (PU0).

  • Page 31: P40 To P47 (port 4)

    2.2.4 P40 to P47 (Port 4) These pins constitute an 8-bit I/O port. In addition, they also function as key return signal detection pins. The following operation modes can be specified in 1-bit units. (1) Port mode In this mode, port 4 functions as an 8-bit I/O port. Port 4 can be set to the input or output mode in 1-bit units by using port mode register 4 (PM4).

  • Page 32: Vpp ( µ Pd78f9801 Only)

    Handle this pin in either of the following ways. • Independently connect a 10 kΩ pull-down resistor. • Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to V normal operation mode using a jumper on the board.

  • Page 33: Pin I/o Circuits And Recommended Connection Of Unused Pins

    2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 lists the types of I/O circuits for each pin and explains how unused pins are handled. Figure 2-1 shows the configuration of each type of I/O circuit. Table 2-1. Type of Pin I/O Circuit Recommended Connection of Unused Pins Pin Name I/O Circuit Type P00 to P07...

  • Page 34: Pin I/o Circuits

    Type 2 Schmitt-triggered input with hysteresis characteristics Type 5-R Pull-up enable P-ch Output data Output disable Input enable Type 8-C Pull-up enable Output data Output disable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 8-F Pull-up enable P-ch Output data Output...

  • Page 35: Chapter 3 Cpu Architecture

    CHAPTER 3 3.1 Memory Space The PD789800 Subseries can access 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. Special function register Internal high-speed RAM Data memory space Program memory space CPU ARCHITECTURE Figure 3-1. Memory Map ( PD789800) 8 bits 8 bits Reserved...

  • Page 36

    Figure 3-2. Memory Map ( PD78F9801) Special function register Internal high-speed RAM Data memory space Program memory space 16,384 CHAPTER 3 CPU ARCHITECTURE 8 bits 8 bits Reserved Flash memory 8 bits User’s Manual U12978EJ3V0UD Program area CALLT table area Program area Vector table area...

  • Page 37: Internal Program Memory Space

    3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The following areas are allocated to the internal program memory space. (1) Vector table area A 26-byte area of addresses 0000H to 0019H is reserved as a vector table area.

  • Page 38: Data Memory Addressing

    3.1.4 Data memory addressing The µ PD789800 Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FFFFH), particular addressing modes are possible to meet the functions of the special function registers (SFR) and general-purpose registers. Figures 3-3 and 3-4 show the data memory addressing modes.

  • Page 39

    CHAPTER 3 Figure 3-4. Data Memory Addressing ( PD78F9801) FFFFH Special function registers (SFR) 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 8 bits FE20H FE1FH FE00H FDFFH Reserved 4000H 3FFFH Flash memory 16,384 8 bits 0000H User’s Manual U12978EJ3V0UD CPU ARCHITECTURE SFR addressing Short direct...

  • Page 40: Processor Registers

    3.2 Processor Registers The µ PD789800 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence, statuses and stack memory. A program counter, a program status word, and a stack pointer are the control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.

  • Page 41

    CHAPTER 3 (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU. When 0, the IE flag is set to the interrupt disabled status (DI), and interrupt requests other than non- maskable interrupts are all disabled. When 1, the IE flag is set to the interrupt enabled status (EI).

  • Page 42: Configuration Of Stack Pointer

    (3) Stack pointer (SP) This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Configuration of Stack Pointer SP15 SP14 SP13 SP12 SP11 SP10 SP9 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory.

  • Page 43: General-purpose Registers

    3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).

  • Page 44: Special Function Registers (sfrs)

    3.2.3 Special function registers (SFRs) Unlike general-purpose registers, each special function register has a special function. The special function registers are allocated in the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions.

  • Page 45: Special Function Register List

    Table 3-2. Special Function Register List (1/3) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF04H Port 4 FF07H Receive data PID FF08H Receive data address 0 FF09H Receive data address 1 FF0AH Receive data address 2 FF0BH Receive data address 3...

  • Page 46

    Table 3-2. Special Function Register List (2/3) Address Special Function Register (SFR) Name FF62H Token packet receive result store register FF63H Data/handshake PID compare register FF64H Data/handshake packet receive byte number counter FF65H Data/handshake packet receive result store register FF66H Data/handshake packet receive mode register FF67H...

  • Page 47

    Table 3-2. Special Function Register List (3/3) Address Special Function Register (SFR) Name FFECH External interrupt mode register 0 FFF5H Key return mode register 00 FFF7H Pull-up resistor option register 0 FFF9H Watchdog timer mode register FFFAH Oscillation stabilization time select register FFFBH Processor clock control register CHAPTER 3...

  • Page 48: Instruction Address Addressing

    3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series Instruction User’s Manual (U11047E)).

  • Page 49: Immediate Addressing

    3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. The CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CHAPTER 3...

  • Page 50: Register Addressing

    3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower-5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.

  • Page 51: Operand Address Addressing

    3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Label or 16-bit immediate data...

  • Page 52: Short Direct Addressing

    3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. An internal high- speed RAM and special function registers (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 53: Special Function Register (sfr) Addressing

    3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.

  • Page 54: Register Addressing

    3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by the register specification code or function name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

  • Page 55: Register Indirect Addressing

    3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.

  • Page 56: Based Addressing

    3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.

  • Page 57: Chapter 4 Port Functions

    4.1 Port Functions The µ PD789800 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS. Port 2 Port 4 CHAPTER 4...

  • Page 58: Functions Of Ports

    Pin Name P00 to Port 0 8-bit I/O port Input/output can be specified in 1-bit units. When used as an input port, use of on-chip pull-up resistors can be specified by pull-up resistor option register 0 (PU0). When used as an output port, CMOS output or N-ch open-drain output can be specified in 8-bit units by port output mode register 0 (POM0).

  • Page 59: Port Configuration

    4.2 Port Configuration Ports consists the following hardware. Parameter Control registers Port mode register (PMm: m = 0 to 2, 4) Pull-up resistor option register (PU0) Port output mode register (POMm: m = 0, 1) Ports Total: 31 (N-ch open-drain output is specifiable for 18 ports.) Pull-up resistors Software control: 31 CHAPTER 4...

  • Page 60: Port 0

    4.2.1 Port 0 This is an 8-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by using port mode register 0 (PM0). When the P00 to P07 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).

  • Page 61: Port 1

    4.2.2 Port 1 This is an 8-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).

  • Page 62: Port 2

    4.2.3 Port 2 This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be connected in 7-bit units by using pull-up resistor option register 0 (PU0).

  • Page 63: Block Diagram Of P21

    CHAPTER 4 Figure 4-5. Block Diagram of P21 PU02 PORT Output latch (P21) PM21 Alternate function PU0: Pull-up resistor option register 0 Port mode register Port 2 read signal Port 2 write signal PORT FUNCTIONS User’s Manual U12978EJ3V0UD P-ch P21/SO10...

  • Page 64: Block Diagram Of P22

    PU02 Alternate function PORT Output latch (P22) PM22 PU0: Pull-up resistor option register 0 Port mode register Port 2 read signal Port 2 write signal CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 User’s Manual U12978EJ3V0UD P-ch P22/SI10...

  • Page 65: Block Diagram Of P23 And P24

    CHAPTER 4 Figure 4-7. Block Diagram of P23 and P24 PU02 PORT Output latch (P23, P24) PM23, PM24 PU0: Pull-up resistor option register 0 Port mode register Port 2 read signal Port 2 write signal PORT FUNCTIONS User’s Manual U12978EJ3V0UD P-ch P23, P24...

  • Page 66: Block Diagram Of P25

    POM1 POM125 PU02 PORT Output latch (P25) PM25 POM1: Port output mode register 1 PU0: Pull-up resistor option register 0 Port mode register Port 2 read signal Port 2 write signal CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P25 User’s Manual U12978EJ3V0UD P-ch P-ch...

  • Page 67: Block Diagram Of P26

    CHAPTER 4 Figure 4-9. Block Diagram of P26 POM1 POM126 PU02 PORT Output latch (P26) PM26 POM1: Port output mode register 1 PU0: Pull-up resistor option register 0 Port mode register Port 2 read signal Port 2 write signal PORT FUNCTIONS User’s Manual U12978EJ3V0UD P-ch P-ch...

  • Page 68: Port 4

    4.2.4 Port 4 This is an 8-bit I/O port with an output latch. Port 4 can be specified in the input or output mode in 1-bit units by using port mode register 4 (PM4). When using P40 to P47 pins as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).

  • Page 69: Registers Controlling Port Function

    4.3 Registers Controlling Port Function The following three types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM4) • Pull-up resistor option register (PU0) • Port output mode registers (POM0, POM1) (1) Port mode registers (PM0, PM1, PM2, PM4) These registers are used to set port input/output in 1-bit units.

  • Page 70: Format Of Pull-up Resistor Option Register 0

    Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Secondary Function Pin Name Name TO01 TI01 INTP0 P40 to KR00 to KR07 Note Note Set key return mode register 00 (KRM00) to 1 when using the alternate function (see Section 11.3 (5) Key return mode register 00 (KRM00)).

  • Page 71: Format Of Port Output Mode Register 0

    (3) Port output mode registers (POM0 and POM1) The port output mode registers (POM0 and POM1) are used to switch from CMOS output to N-ch open-drain output for port 0, port 1, pin P25, and pin P26. Set POM0 and POM1 with a 1-bit or 8-bit memory manipulation instruction.

  • Page 72: Port Function Operation

    4.4 Port Function Operation The operation of a port differs depending on whether the port is set to the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.

  • Page 73: Chapter 5 Clock Generator

    CHAPTER 5 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is used. • • • • System clock oscillator This circuit oscillates at 6.0 MHz. Oscillation can be stopped by executing the STOP instruction. 5.2 Clock Generator Configuration The clock generator consists of the following hardware.

  • Page 74: Register Controlling Clock Generator

    5.3 Register Controlling Clock Generator The clock generator is controlled by the following register. • Processor clock control register (PCC) (1) Processor clock control register (PCC) PCC selects the CPU clock and sets the of division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 02H.

  • Page 75: System Clock Oscillators

    5.4 System Clock Oscillators 5.4.1 System clock oscillator The system clock oscillator is oscillated by the crystal resonator (6.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and leave the X2 pin open.

  • Page 76: Examples Of Incorrect Resonator Connection

    5.4.2 Examples of incorrect resonator connection Figure 5-4 shows examples of incorrect resonator connection. Figure 5-4. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (c) Wiring near high fluctuating current CHAPTER 5 CLOCK GENERATOR (b) Crossed signal line (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current...

  • Page 77: Frequency Divider

    Figure 5-4. Examples of Incorrect Resonator Connection (2/2) 5.4.3 Frequency divider The frequency divider divides the output of the system clock oscillator (f 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode.

  • Page 78: Changing Setting Of Cpu Clock

    5.6 Changing Setting of CPU Clock 5.6.1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed; the old clock is used for the duration of several instructions after that (see Table 5-2).

  • Page 79: 8-bit Timer/event Counters 00 And 01

    CHAPTER 6 6.1 Functions of 8-Bit Timer/Event Counters 00 and 01 The 8-bit timer/event counters (TM00 and TM01) have the following functions. • Interval timer (TM00 and TM01) • External event counter (TM01 only) • Square wave output (TM01 only) The µ...

  • Page 80: Configuration Of 8-bit Timer/event Counters 00 And 01

    CHAPTER 6 (3) Square wave output A square wave of arbitrary frequency can be output. Table 6-3. Square Wave Output Range of 8-Bit Timer/Event Counter 01 Minimum Pulse Width (2.67 µ s) (42.7 µ s) Remarks 1. f : System clock oscillation frequency 2.

  • Page 81: Block Diagram Of 8-bit Timer/event Counter 01

    CHAPTER 6 Figure 6-2. Block Diagram of 8-Bit Timer/Event Counter 01 8-bit compare register 01 8-bit timer counter 01 TI01/P26 /INTP0/TO01 (1) 8-bit compare register 0n (CR0n) This is an 8-bit register used to compare the value set to CR0n with the 8-bit timer counter 0n (TM0n) count value, and if they match, generate used an interrupt request (INTTM0n).

  • Page 82: Registers Controlling 8-bit Timer/event Counters 00 And 01

    CHAPTER 6 6.3 Registers Controlling 8-Bit Timer/Event Counters 00 and 01 The following two types of registers are used to control 8-bit timer/event counters 00 and 01. • 8-bit timer mode control registers 00 and 01 (TMC00 and TMC01) • Port mode register 2 (PM2) (1) 8-bit timer mode control register 00 (TMC00) This register enables/stops operation of 8-bit timer counter 00 (TM00) and sets the counter clock of 8-bit timer TMC00 is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 83: Format Of 8-bit Timer Mode Control Register 01

    CHAPTER 6 (2) 8-bit timer mode control register 01 (TMC01) TMC01 determines whether to enable or disable 8-bit timer counter 01 (TM01), specifies the count clock for the 8-bit timer/event counter, and controls the operation of the output controller. TMC01 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC01 to 00H.

  • Page 84: Format Of Port Mode Register 2

    CHAPTER 6 (3) Port mode register 2 (PM2) This register sets port 2 input/output in 1-bit units. When using the P26/TO01/INTP0/TI01 pin for timer output, set P26 and the output latch of P26 to 0. When P26/TO01/INTP0/TI01 pin is used as a timer input, set PM26 to 1. PM2 is set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 85: Operation Of 8-bit Timer/event Counters 00 And 01

    CHAPTER 6 6.4 Operation of 8-Bit Timer/Event Counters 00 and 01 6.4.1 Operation as interval timer Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare registers 00 and 01 (CR00 and CR01) in advance. To operate the 8-bit timer/event counter as an interval timer, the following settings are required.

  • Page 86: Interval Timer Operation Timing Of 8-bit Timer 00

    CHAPTER 6 Figure 6-6. Interval Timer Operation Timing of 8-Bit Timer 00 Count clock TM00 count value CR00 TCE00 Count starts INTTM00 Interval time Interval time = (N + 1) × t where N = 00H to FFH Remark Figure 6-7. Interval Timer Operation Timing of 8-Bit Timer/Event Counter 01 Count clock TM01 count value CR01...

  • Page 87: Operation As External Event Counter (timer 01 Only)

    CHAPTER 6 6.4.2 Operation as external event counter (timer 01 only) The external event counter counts the number of external clock pulses input to the TI01/P26/INTP0/TO01 pin by using timer counter 01 (TM01). To operate the 8-bit timer/event counter as an external event counter, the following settings are required. <1>...

  • Page 88: Operation As Square-wave Output (timer 01 Only)

    CHAPTER 6 6.4.3 Operation as square-wave output (timer 01 only) The 8-bit timer/event counter can generate output square waves of arbitrary frequency at intervals specified by the count value set to 8-bit compare register 01 (CR01) in advance. To operate 8-bit timer/event counter 01 as square wave output, the following settings are required. <1>...

  • Page 89: Timing Of Square-wave Output

    CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-9. Timing of Square-Wave Output Count clock TM01 count value Clear Clear CR01 TCE01 Count start INTTM01 Interrupt acknowledged Interrupt acknowledged Note TO01 Note The initial value of TO01 when output is enabled (TOE01 = 1) becomes low level. User’s Manual U12978EJ3V0UD...

  • Page 90: Notes On Using 8-bit Timer/event Counters 00 And 01

    CHAPTER 6 6.5 Notes on Using 8-Bit Timer/Event Counters 00 and 01 (1) Error on starting timer An error of up to 1 clock occurs after the timer is started until a match signal is generated. This is because 8-bit timer counters 00 and 01 (TM00 and TM01) are started asynchronously to the count pulse.

  • Page 91: Chapter 7 Watchdog Timer

    CHAPTER 7 7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect inadvertent program loops.

  • Page 92: Watchdog Timer Configuration

    7.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 7-3. Configuration of Watchdog Timer Item Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 7-1. Block Diagram of Watchdog Timer Prescaler TCL22 TCL21 TCL20 Timer clock select register 2 (TCL2)

  • Page 93: Registers Controlling Watchdog Timer

    7.3 Registers Controlling Watchdog Timer The following two registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction.

  • Page 94: Format Of Watchdog Timer Mode Register

    (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. The WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the WDTM to 00H. Figure 7-3.

  • Page 95: Watchdog Timer Operation

    7.4 Watchdog Timer Operation 7.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).

  • Page 96: Operation As Interval Timer

    7.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance.

  • Page 97: Chapter 8 Usb Function

    8.1 USB Overview The USB (Universal Serial Bus) is suitable for connecting personal computers and external devices such as audio equipment, keyboards, pointing devices, and telephones. Two data transfer rates, 12 Mbps and 1.5 Mbps, are provided. Plug & Play can also be realized. Figure 8-1 shows an example of USB connection to a desktop PC.

  • Page 98: Usb Function Features

    8.2 USB Function Features The features of the on-chip USB function provided for the µ PD789800 Subseries are described below. (1) Video display devices and human interface devices are assumed to be the target applications. For this reason, only Endpoint 0 for control transfer and Endpoint 1 for interrupt transfer are supported. (2) 1.5 Mbps (low speed) data transfer using a 6.0 MHz system clock is supported.

  • Page 99: Block Diagram Of Usb Function

    Figure 8-2. Block Diagram of USB Function USB receiver Data/handshake enable register packet receive mode register (URXMOD) (USBMOD) Remote wakeup control register (REMWUP) EOP generation/detection USBDP Resume & reset detection control SYNC detection/ USBDM USB clock generator USB clock Note 4 USB timer (7-bit counter) Start...

  • Page 100: Block Diagram Of Usb Timer

    Figure 8-3. Block Diagram of USB Timer INTUSBTM Note RESUME RX Clock controller USBCLK DATATX SETORX USB timer start reservation control register (USBTCL) Internal bus Note As these signals are used internally, confirmation by software is not possible. Remark f System clock oscillation frequency UWDERR: Bit 7 of packet receive status register (RXSTAT) CHAPTER 8...

  • Page 101

    (1) Receive bank switching ID detection buffer (internal buffer) This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID during packet reception and determines the store bank of a packet. The following controls are performed depending on the stored 2-bit data.

  • Page 102: Configuration Of Receive Token Bank

    (3) Receive token bank (a) Receive token PID (USBRTP) This is the receive token packet ID area. The data input to the token PID compare register (TIDCMP) is stored here. USBRTP is read with an 8-bit memory manipulation instruction. RESET input sets USBRTP to 00H. (b) Receive token address L and H (USBRAL and USBRAH) This stores the token packet to be transferred from the host.

  • Page 103: Configuration Of Receive Data Bank

    (4) Receive data bank (a) Receive data PID (USBRD) This is the receive data packet ID area. The data input to the data/handshake PID compare register (DIDCMP) is stored here. USBRD is read with an 8-bit memory manipulation instruction. RESET input sets USBRD to 00H. (b) Receive data address (USBR0 to USBR7) This is an 8-byte register that stores the data/handshake packet transferred from the host.

  • Page 104: Configuration Of Transmit Data Bank 0 (buffer 0)

    (5) Transmit data banks 0 and 1 (a) Transmit data PID banks 0 and 1 (USBTD0 and USBTD1) USBTD0 and USBTD1 correspond to the transmit buffer 0 ID area and transmit buffer 1 ID area, respectively. USBTD0 and USBTD1 store DATA0 (C3H) or DATA1 (4BH). USBTD0 and USBTD1 are set with an 8-bit memory manipulation instruction.

  • Page 105: Configuration Of Transmit Data Bank 1 (buffer 1)

    Figure 8-7. Configuration of Transmit Data Bank 1 (Buffer 1) Symbol USBTD1 USBT10 USBT11 USBT12 USBT13 USBT14 USBT15 USBT16 USBT17 The operation during transmission appears as follows. Packet from host controller Response packet 1st byte USBT00 8th byte USBT07 USBT10 USBT17 Data is read according to the data sequence in the control read data stage and is transmitted to the host.

  • Page 106

    (6) Data/handshake packet receive byte number counter (DRXCON) This register sets the number of data of the data/handshake packet to be received. During data/handshake packet reception, if this register value and the transmit/receive pointer (USBPOW) value match, a match signal is output from the comparator.

  • Page 107: Configuration Of Tidcmp And Adrcmp

    (9) Token address compare register (ADRCMP) This register sets the address specified from the host during control transfer. If this register value and the address area of the receive token bank (bits 0 to 6 of receive token address L (USBRAL)) match during token packet reception coincide, ADRRST (bit 2 of the token packet receive result store register (TRXRSL)) is set.

  • Page 108: Configuration Of Didcmp

    (10) Data/handshake PID compare register (DIDCMP) This register sets the data/handshake packet ID to be received. If this register value and the value of the receive data PID (USBRD) match during data/handshake packet reception coincide, the DIDRST (bit 1 of the data/handshake packet receive result store register (DRXRSL)) is set.

  • Page 109: Registers Controlling Usb Function

    Bit 1 (DINTEN) is a flag used to set the receive status synchronous interrupt (to generate the INTUSBRD interrupt request to perform data packet reception and data save simultaneously). Bit 2 (RESMOD) is a flag used to switch the detection mode of the USB reset signal between bus idle mode and bus suspend mode.

  • Page 110: Format Of Data/handshake Packet Receive Mode Register

    Figure 8-11. Format of Data/Handshake Packet Receive Mode Register Symbol URXMOD RESMOD Reject USB reset signal less than 3.0 s SE0 (Single-ended 0) period. Detect transition from J state to SE0 as USB reset signal. DINTEN Do not generate data packet receive status synchronous interrupt. Generate data packet receive status synchronous interrupt DWRMSK Enable write operation to all addresses in data/handshake packet receive buffer.

  • Page 111

    CHAPTER 8 USB FUNCTION (3) Packet receive status register (RXSTAT) This register indicates the receive status of each packet. Bits 0 to 2 (TOSTAT, DASTAT, and HSSTAT) are flags that indicate that a token packet, data packet, or handshake packet is currently being received. These flags are set upon detection of a packet ID by an ID detection buffer, and cleared upon reception of EOP.

  • Page 112: Format Of Packet Receive Status Register

    Figure 8-12. Format of Packet Receive Status Register Symbol RXSTAT UWDERR RESMRX SE0RX URESRX EOPRX HSSTAT DASTAT TOSTAT UWDERR No USB timer inadvertent program loop was detected. USB timer inadvertent program loop (USB clock operation faster than 85.3 s (at 6.0 MHz)) was detected, forcibly terminating USB clock.

  • Page 113: Format Of Data/handshake Packet Receive Result Store Register

    Table 8-2 shows the state of each flag after receiving the USB reset signal and the Resume signal during the bus idle state and bus suspend state. Table 8-2. Flag of RXSTAT After Reception of USB Reset Signal and Resume Signal Bus State Device State Idle...

  • Page 114: Format Of Token Packet Receive Result Store Register

    Figure 8-14. Format of Token Packet Receive Result Store Register Symbol <7> <6> <5> TRXRSL CRC5ER TBITER TBYER END1RX END0RX ADRRST TIDRST CRC5ER CRC error did not occur in received token packet. CRC error occurred in received token packet. TBITER Bit stuffing error did not occur in received token packet.

  • Page 115: Format Of Data Packet Transmit Reservation Register

    (6) Data packet transmit reservation register (DTXRSV) This register sets the bank where the data packet to be transmitted is stored. By setting each flag of this register, the stored data is transmitted following normal reception of the IN token packet. DTXRSV is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 116: Format Of Handshake Packet Transmit Reservation Register

    (7) Handshake packet transmit reservation register (HTXRSV) This register sets the handshake packet to be transmitted. By setting each flag of this register, a handshake packet is transmitted following normal reception of an IN packet, or normal or abnormal reception of a data packet.

  • Page 117: Conditions In Transmit Reservation

    Figure 8-16. Format of Handshake Packet Transmit Reservation Register (2/2) E1NAEN NAK packet transmit reservation flag for Endpoint 1 after IN packet No data is transmitted. NAK handshake is transmitted when all the following conditions are satisfied in EOP during IN packet reception. INRX (internal signal) = 1, ADRRST = 1, END1RX = 1, TBYER = 0, TBITER = 0, CRC5ER = 0 E0NAEN NAK packet transmit reservation flag for Endpoint 0 after IN packet...

  • Page 118

    Table 8-3. Conditions in Transmit Reservation (2/2) (b) Transmit reservation for Endpoint1 and IN token packet Type of Reservation Transmit reservation of data in transmit buffer 0 Transmit reservation of data in transmit buffer 1 Endpoint 1 STALL transmit reservation (halt status) Endpoint 1 NAK transmit reservation (no transmit data)

  • Page 119: Configuration Of Handshake Packet Transmit Reservation Register

    Figure 8-17. Configuration of Handshake Packet Transmit Reservation Register E1STEN Note MASTER EN Note Because these signals are used internally, confirmation by software is not possible. CHAPTER 8 USB FUNCTION E0STEN DSTEN STALEN E1NAEN E0NAEN DNAEN User’s Manual U12978EJ3V0UD ACKEN END1RX END0RX Note...

  • Page 120: Format Of Usb Timer Start Reservation Control Register

    (8) USB timer start reservation control register (USBTCL) This register reserves USB timer start after reception of a SETUP/OUT packet or transmission of a data packet. USBTCL is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets USBTCL to 01H. Note SETUP reception also sets USBTCL to 01H.

  • Page 121: Format Of Remote Wakeup Control Register

    (9) Remote wake-up control register (REMWUP) This register transmits the Resume signal to perform remote wakeup. Remote wakeup must be performed after confirming that bus idle has continued longer than 5 ms. REMWUP is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets REMWUP to 08H.

  • Page 122: Usb Function Operation

    8.5 USB Function Operation 8.5.1 USB timer operation The USB timer is a 7-bit counter that performs time management during packet transmission and reception and inadvertent program loop detection of the USB clock. The USB timer has two modes: high-speed mode (source clock = f clock: f = 1.5 MHz during 6.0 MHz operation).

  • Page 123: Flowchart Of Usb Timer Operation

    Figure 8-20. Flowchart of USB Timer Operation (1/2) Idle state SYNC detected? USB timer reset USB timer start (low-speed mode) EOP received? USB timer reset SETUP/OUT packet? SETORX (internal signal) = 1? UWDERR: Bit 7 of packet receive status register (RXSTAT) CHAPTER 8 USB FUNCTION INTUSBTM occurred...

  • Page 124

    CHAPTER 8 USB FUNCTION Figure 8-20. Flowchart of USB Timer Operation (2/2) USB timer start (high-speed mode) Next SYNC detected? High-speed mode overflow? INTUSBTM occurred User’s Manual U12978EJ3V0UD...

  • Page 125: Remote Wakeup Control Operation

    8.5.2 Remote wakeup control operation Figure 8-21. Flow Chart of Remote Wakeup Control Operation Resume Note 1 output Resume output Note 2 completion PULLDP: Bit 2 of remote wakeup control register (REMWUP) PULLDM: Bit 3 of remote wakeup control register (REMWUP) PULLEN: Bit 1 of remote wakeup control register (REMWUP) WAKEUP: Bit 0 of remote wakeup control register (REMWUP)

  • Page 126: Configuration Of Remote Wakeup Control

    Notes 1. Be sure to follow the exact instruction sequence when the Resume signal (“K” state) is output. SET1 REMWUP.3 CLR1 REMWUP.2 A, #00000111B ; (A ← 00000111B) SET1 REMWUP.1 SET1 REMWUP.0 REMWUP, A 2. Be sure to follow the exact instruction sequence to append EOP when terminating Resume output. CLR1 REMWUP.0 CLR1...

  • Page 127: Interrupt Request From Usb Function

    8.6 Interrupt Request from USB Function 8.6.1 Interrupt sources Interrupt request sources generated by the USB function fall into the following five categories. Table 8-4. List of Sources of Interrupts from USB Function Note Type of Interrupt Priority Name Maskable INTUSBTM INTUSBRT INTUSBRD...

  • Page 128: Timing Of Intusbre Generation

    (3) Data/handshake packet transmit interrupt (INTUSBST) Upon EOP detection during data/handshake packet transmission, an interrupt request signal is generated and an interrupt request flag (USBSTIF) is set. (4) USB timer overflow interrupt (INTUSBTM) If the USB timer overflows, an interrupt request signal is generated and an interrupt request flag (USBTMIF) is set.

  • Page 129: Cautions When Using Interrupts

    8.6.2 Cautions when using interrupts Pay attention to the following when using an interrupt request generated by the USB function. (1) Because USBREIF is set by transition from the J state to the K state on the bus, it is also set during sync detection or packet reception.

  • Page 130: Usb Function Control

    8.7 USB Function Control 8.7.1 Relationship between packets and operation modes The relationship between packets and operation modes in the USB function is as follows. (1) Control transfer (OUT) (Transfer byte count: 8 bytes or less) Packet flow Packet from Packet from µ...

  • Page 131

    (2) Control transfer (OUT) (Transfer byte count: 9 bytes or more) Packet flow Packet from Packet from µ PD789800 host controller SETUP Setup stage DATA0 Data stage OUT reception DATA1 DATA0 DATA1 DATA1/0 Status stage IN reception DATA1 CHAPTER 8 USB FUNCTION Operation of host controller...

  • Page 132

    (3) Control transfer (IN) (Transfer byte count: 8 bytes or less) Packet flow Packet from Packet from µ PD789800 host controller SETUP Setup stage DATA0 Data stage IN reception DATA1 DATA1 Status stage OUT reception reception wait Note If the ACK from the device cannot be received normally, the host transmits OUT again. Therefore, set the OUT receive wait state for a period so that the OUT can be received.

  • Page 133

    (4) Control transfer (IN) (Transfer byte count: 9 bytes or more) Packet flow Packet from Packet from µ PD789800 host controller SETUP Setup stage DATA0 Data stage IN reception DATA1 DATA0 DATA0/1 Status DATA1 stage OUT reception reception wait Note If the ACK from the device cannot be received normally, the host transmits OUT again. Therefore, set the OUT receive wait state for a period so that the OUT can be received.

  • Page 134

    (5) No data control Packet flow Packet from Packet from µ PD789800 host controller Setup SETUP stage DATA0 Status stage No data control DATA1 CHAPTER 8 USB FUNCTION Operation of host controller Request IN packet ACK packet User’s Manual U12978EJ3V0UD Operation of USB µ...

  • Page 135

    (6) Interrupt transfer Packet flow Packet from Packet from µ host controller PD789800 DATA1 DATA0 CHAPTER 8 USB FUNCTION Operation of host controller IN packet IN packet IN packet IN packet User’s Manual U12978EJ3V0UD Operation of USB µ function of PD789800 ACK transmission reservation •...

  • Page 136: Interrupt Servicing Flow

    8.7.2 Interrupt servicing flow (1) USB token packet reception interrupt servicing INTUSBRT occurrence Receive error occurred? Receive token is OUT? Receive token is SETUP? Receive token is unplanned token? SETUP token reception processing IN token reception processing to ENDPOINT 0 IN token reception processing to ENDPOINT 1 CHAPTER 8...

  • Page 137

    (2) Data/handshake packet reception interrupt servicing INTUSBRD occurrence Planned packet was received? USB_MODE is data stage OUT reception? Re-transmit data reception reservation processing RETI CHAPTER 8 USB FUNCTION Transition processing to status stage OUT reception USB_MODE is SETUP? USB request processing DATA/ACK reception processing to ENDPOINT 0 User’s Manual U12978EJ3V0UD...

  • Page 138

    (3) USB timer inadvertent program loop detection interrupt servicing CHAPTER 8 USB FUNCTION INTUSBTM occurrence Processing for each operation mode when ACK is not received and for when DATA is not received after receiving OUT RETI User’s Manual U12978EJ3V0UD...

  • Page 139

    (4) 1 ms timer interrupt servicing INTTM00 occurrence DURATION base timer processing 10 ms timer counting USB communication completion timer processing Waiting for resume signal completion? RESET received? Communication operating? Standby detected? Standby processing REMOTE WAKEUP? RESUME output processing RETI CHAPTER 8 USB FUNCTION USB reset processing...

  • Page 140: Usb Function Internal Circuit Operations

    8.8 USB Function Internal Circuit Operations 8.8.1 Operation of transmit/receive pointer Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (1/7) (1) Token packet reception (1/2) Idle state Transmit/receive signal? Token reception Set USBPOW to 00H Set USBPOB to 00H Bit normal write? Set TBYER flag Does bit stuffing signal = 1?

  • Page 141

    Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (2/7) (1) Token packet reception (2/2) TBYER: Bit 5 of token packet receive result store register (TRXRSL) CHAPTER 8 USB FUNCTION Bit normal write? Set TBYER flag Does bit stuffing signal = 1? Idle state USBPOB increment USBPOW...

  • Page 142

    Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (3/7) (2) Data/Handshake packet reception (1/2) Idle state Transmit/receive signal? Data/handshake reception Set USBPOW to 10H Set USBPOB to 00H Does USBPOW match DRXCON? Bit normal write? Does bit stuffing signal = 1? USBPOB increment USBPOB overflow?

  • Page 143

    Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (4/7) (2) Data/Handshake packet reception (2/2) USBPOW increment DBYER: Bit 5 of data/handshake packet receive result store register (DRXRSL) CHAPTER 8 USB FUNCTION Bit normal write? Set DBYER flag Does bit stuffing signal = 1? Idle state USBPOB increment USBPOB...

  • Page 144

    Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (5/7) (3) Data packet transmit (1/2) Idle state Transmit/receive signal? Data/handshake transmission Set USBPOW to 7FH Set USBPOB to 00H Bit read Does bit stuffing signal = 1? USBPOB increment USBPOB overflow? Handshake Transmit area? Go to (4) (reservation flag...

  • Page 145

    Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (6/7) (3) Data packet transmit (2/2) Bit Read Does bit stuff signal = 1? USBPOB increment USBPOB overflow? Set USBPOW to 70H Read CRC redundant bit Does bit stuffing signal = 1? USBPOB increment USBPOB overflow? USBPOW increment...

  • Page 146

    Figure 8-25. Flowchart of Transmit/Receive Pointer Operation (7/7) (4) Handshake packet transmission Idle state Transmit/receive signal? Data/handshake transmission Set USBPOW to 7FH Set USBPOB to 00H Bit read Does bit stuffing signal = 1? USBPOB increment USBPOB overflow? Transmit buffer Transmit area? (reservation flag judgment)

  • Page 147: Receive Bank Switching Id Detection Buffer Operation

    8.8.2 Receive bank switching ID detection buffer operation Figure 8-26. Flowchart of Receive Bank Switching ID Detection Buffer Operation Idle state Sync1 detection signal = 1? 2-bit store & shift Bit judgment enable Store bit ? Set TOSTAT Bit judgment mask 1-bit store &...

  • Page 148: Sync Detection/usbclk Detector Operation

    8.8.3 Sync detection/USBCLK detector operation This circuit generates the USBCLK signal (1.5 MHz) upon detecting the sync part of the receive packet. In addition, it contains an NRZI decoder that decodes receive packets and detects the last bit of the sync part. When the last sync bit is detected, a signal that specifies start of storing in the ID detection buffer is output.

  • Page 149: Flowchart Of Sync Detection/usbclk Detector Operation

    CHAPTER 8 USB FUNCTION Figure 8-29. Flowchart of Sync Detection/USBCLK Detector Operation Idle state Did state change to K state? USB clock oscillation start Output 0 from NRZI decoder Receive next bit Did bus state change? Output 1 from NRZI decoder Detect last Sync bit Was EOP receive signal set?

  • Page 150: Nrzi Encoder Operation

    8.8.4 NRZI encoder operation This circuit performs NRZI encoding of data to be transmitted. Figure 8-30. Timing of NRZI Encoder Operation Data before encoding NRZI encoding Transmit packet USB clock generation Figure 8-31. Flow Chart of NRZI Encoder Operation Reverse output level Reverse output level EOP transmit signal CHAPTER 8...

  • Page 151: Bit Stuffing/strip Controller Operation

    8.8.5 Bit stuffing/strip controller operation This circuit counts the number of “logic 1” of transmit/receive packets. If six successive logic 1s are detected, it outputs an increment disable signal to the transmit/receive pointer (USBPOB). During packet transmission, it inserts “logic 0” simultaneously with the increment disable signal. Moreover, during bit stripping, if the bit that should be deleted was a “logic 1,”...

  • Page 152: Flow Chart Of Bit Stuffing Control Operation

    Figure 8-33. Flow Chart of Bit Stuffing Control Operation CHAPTER 8 USB FUNCTION Idle state Transmission start? Transmit bit input Transmit bit = 1? Shift bit Reset bit stuffing register stuffing register Bit stuffing register = 3FH? Disable USBPOB increment Reset bit stuffing register Disable save...

  • Page 153: Flow Chart Of Bit Strip Control Operation

    CHAPTER 8 USB FUNCTION Figure 8-34. Flow Chart of Bit Strip Control Operation Idle state Reception start? Receive bit input Receive bit = 1? Shift bit stuffing register Bit stuffing register = 3FH? Disable USBPOB increment EOP receive signal set? Receive bit input Receive bit = 1? Reset bit...

  • Page 154: Serial Interface 10

    The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer processing time. It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing connection to devices with either start bit.

  • Page 155: Configuration Of Serial Interface 10

    9.2 Configuration of Serial Interface 10 Serial interface 10 consists of the following hardware. Table 9-1. Configuration of Serial Interface 10 Item Register Transmit/receive shift register 10 (SIO10) Control register Serial operating mode register 10 (CSIM10) (1) Transmit/receive shift register 10 (SIO10) This is an 8-bit register used for parallel-to-serial conversion and to perform serial data transmission/reception in synchronization with the serial clock.

  • Page 156: Block Diagram Of Serial Interface 10

    SI10/P22 SO10/P21 SCK10/P20 Figure 9-1. Block Diagram of Serial Interface 10 Internal bus Serial operation mode register 10 (CSIM10) CSIE10 TPS100 DIR10 CSCK10 Serial clock counter Clock controller Transmit/receive shift register 10 (SIO10) Interrupt request generator INTCSI10...

  • Page 157: Register Controlling Serial Interface 10

    9.3 Register Controlling Serial Interface 10 The following register is used to control serial interface 10. • Serial operation mode register 10 (CSIM10) (1) Serial operation mode register 10 (CSIM10) This register is used to control serial interface 10 and set the serial clock and start bit. CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

  • Page 158: Operating Mode Settings Of Serial Interface 10

    Table 9-2. Operating Mode Settings of Serial Interface 10 (1) Operation stop mode CSIM10 PM22 PM21 CSIE10 DIR10 CSCK10 × × × Note 1 × Note 1 × Other than above (2) 3-wired serial I/O mode CSIM10 PM22 PM21 CSIE10 DIR10 CSCK10 ×...

  • Page 159: Operation Of Serial Interface 10

    9.4 Operation of Serial Interface 10 Serial interface 10 provides the following two modes. • Operation stop mode • 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced. The P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports.

  • Page 160: 3-wire Serial I/o Mode

    9.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous serial interface, such as the 75XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10).

  • Page 161: Wire Serial I/o Mode Timing

    (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. transmitted/received bit by bit in synchronization with the serial clock. Transmit/receive shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the serial clock (SCK10).

  • Page 162: Chapter 10 Regulator

    The µ PD789800 incorporates a regulator that powers the USB driver/receiver. The features are as follows. • Generates V (3.3 ±0.3 V) from V • Supports power-saving mode, reducing power consumption in mode. Figure 10-1. Block Diagram of Regulator and USB Driver/Receiver µ...

  • Page 163: Chapter 11 Interrupt Functions

    CHAPTER 11 11.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does no undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.

  • Page 164: Interrupt Source List

    Note 1 Type of Interrupt Priority Name Nonmaskable INTWDT Maskable INTWDT INTUSBTM INTUSBRT INTUSBRD INTUSBST INTUSBRE INTP0 INTCSI10 INTTM00 INTTM01 INTKR00 Notes 1. The priority is the order of priority when multiple maskable interrupts are generated simultaneously. 0 is the highest priority and 10 is the lowest. 2.

  • Page 165: Basic Configuration Of Interrupt Function

    CHAPTER 11 Figure 11-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Interrupt request (B) Internal maskable interrupt Interrupt request (C) External maskable interrupt INTM0, KRM00 Interrupt Edge request detector Interrupt request flag Interrupt enable flag Interrupt mask flag INTM0: External interrupt mode register 0 KRM00: Key return mode register 00...

  • Page 166: Registers Controlling Interrupt Function

    11.3 Registers Controlling Interrupt Function The following five registers are used to control the interrupt functions. • Interrupt request flag registers 0 and 1 (IF0 and IF1) • Interrupt mask flag registers 0 and 1 (MK0 and MK1) • External interrupt mode register 0 (INTM0) •...

  • Page 167: Format Of Interrupt Request Flag Register

    (1) Interrupt request flag registers (IF0 and IF1) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input.

  • Page 168: Format Of Interrupt Mask Flag Register

    (2) Interrupt mask flag registers (MK0 and MK1) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 and MK1 to FFH. Figure 11-3.

  • Page 169: Configuration Of Program Status Word

    (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped here. Besides 8-bit unit read/write, this register can carry out operations with bit manipulation instructions and dedicated instructions (EI, DI).

  • Page 170: Format Of Key Return Mode Register 00

    (5) Key return mode register 00 (KRM00) This register sets the pin that detects a key return signal (rising edge of port 4). KRM00 is set with a 1-bit an 8-bit memory manipulation instruction. Bit 0 (KRM000) is set in 4-bit units for the KR00/P40 to KR03/P43 pins. Bits 4 to 7 (KRM004 to KRM007) are set in 1-bit units for the KR04/P44 to KR07/P47 pins, respectively.

  • Page 171: Interrupt Servicing Operation

    11.4 Interrupt Servicing Operation 11.4.1 Non-maskable interrupt acknowledgment operation The non-maskable interrupt is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.

  • Page 172: Flowchart Of Non-maskable Interrupt Request Acknowledgment

    Figure 11-8. Flowchart of Non-Maskable Interrupt Request Acknowledgment (watchdog timer mode (non-maskable interrupt Interrupt request is generated Interrupt servicing is started WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 11-9. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction TMIF4 Figure 11-10.

  • Page 173: Maskable Interrupt Acknowledgment Operation

    11.4.2 Maskable interrupt acknowledgment operation A maskable interrupt can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1).

  • Page 174: Timing Of Interrupt Request Acknowledgment (example Of Mov A,r)

    Figure 11-12. Timing of Interrupt Request Acknowledgment (Example of MOV A,r) Clock MOV A,r Interrupt When an interrupt request flag (xxIF) is generated before clock n (n = 4 to 10) of the instruction being executed turns to n - 1, the interrupt is acknowledged after the instruction has been executed. Figure 11-12 shows an example for 8-bit data transfer instruction MOV A,r.

  • Page 175: Multiplexed Interrupt Servicing

    11.4.3 Multiplexed interrupt servicing Servicing in which another interrupt is acknowledged while an interrupt is being processed is called multiplexed interrupt servicing. Multiplexed interrupt is not performed unless interrupt requests are enabled (IE = 1) (except the non-maskable interrupt request). Other interrupt requests are disabled (IE = 0) as soon as an interrupt request is acknowledged. Therefore, it is necessary to set (1) the IE flag to realize the interrupt enable state using the EI instruction during interrupt request servicing in order to enable multiplexed interrupt servicing.

  • Page 176: Example Of Multiplexed Interrupt Servicing

    Figure 11-14. Example of Multiplexed Interrupt Servicing Example 1. Acknowledging multiplexed interrupts Main processing IE = 0 INTxx The interrupt request INTyy is acknowledged and multiplexed interrupt servicing is performed during the interrupt INTxx servicing. Before each interrupt is acknowledged, the IE instruction is issued and interrupt requests are enabled.

  • Page 177: Interrupt Request Hold

    11.4.4 Interrupt request hold If an interrupt (such as a maskable, non-maskable, or external interrupt) is requested when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions include: •...

  • Page 178: Chapter 12 Standby Function

    CHAPTER 12 12.1 Standby Function and Configuration 12.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating.

  • Page 179: Register Controlling Standby Function

    12.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 2 Figure 12-1.

  • Page 180: Standby Function Operation

    12.2 Standby Function Operation 12.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 12-1. HALT Mode Operation Status Item Clock generator Port (output latch) 8-bit timer 00 (TM00)

  • Page 181: Releasing Halt Mode By Interrupt

    (2) Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed.

  • Page 182: Releasing Halt Mode By Reset Input

    (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 12-3. Releasing HALT Mode by RESET Input HALT instruction RESET...

  • Page 183: Stop Mode

    12.2.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally pulled up to V current leakage of the crystal oscillator block. Therefore, do not use the STOP mode in a system where an external clock is used as the system clock.

  • Page 184: Releasing Stop Mode By Interrupt

    (2) Releasing STOP mode The STOP mode can be released by the following two sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed.

  • Page 185: Releasing Stop Mode By Reset Input

    (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 12-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operation mode Oscillation Clock...

  • Page 186: Chapter 13 Reset Function

    CHAPTER 13 The following two operations are available to generate reset signals. (1) External reset input via RESET pin (2) Internal reset by inadvertent program loop time detected by watchdog timer External and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.

  • Page 187: Reset Timing By Reset Input

    Figure 13-2. Reset Timing by RESET Input During normal operation RESET Internal reset signal Delay Port pin Figure 13-3. Reset Timing by Overflow in Watchdog Timer During normal operation Overflow in watchdog timer Internal reset signal Port pin Figure 13-4. Reset Timing by RESET Input in STOP Mode STOP instruction execution During normal Stop status...

  • Page 188: Hardware Status After Reset

    Table 13-1. Hardware Status After Reset (1/2) Note 1 Program counter (PC) Stack pointer (SP) Program status word (PSW) Port (P0 to P2, P4) output latch Port mode register (PM0 to PM2, PM4) Pull-up resistor option register (PU0) Port output mode register (POM0, POM1) Processor clock control register (PCC) Oscillation stabilization time select register (OSTS) 8-bit timer/event counter...

  • Page 189

    Table 13-1. Hardware Status After Reset (2/2) USB function Serial interface Interrupt CHAPTER 13 RESET FUNCTION Hardware Data packet transmit byte number counter 0 (DTXCO0) Data packet transmit byte number counter 1 (DTXCO1) Token PID compare register (TIDCMP) Token address compare register (ADRCMP) USB receiver enable register (USBMOD) Packet receive status register (RXSTAT) Data/handshake packet receive result store register...

  • Page 190: µ µ µ µ Pd78f9801

    The µ PD78F9801 is a product that substitutes flash memory for the internal ROM of the mask ROM version. The differences between the µ PD78F9801 and the mask ROM versions are shown in Table 14-1. Table 14-1. Differences Between µ µ µ µ PD78F9801 and Mask ROM Versions Item Internal memory High-speed RAM...

  • Page 191: Flash Memory Characteristics

    14.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the µ PD78F9801 mounted on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used exclusively for programming, is also provided.

  • Page 192: Communication Mode

    14.1.2 Communication mode Use the communication mode shown in Table 14-2 to perform communication between the dedicated flash programmer and µ PD78F9801. Communication Mode COMM PORT SIO Clock 3-wire serial SIO ch-0 100 Hz to (3-wire, sync.) 1.25 MHz Pseudo-3-wire Port A 100 Hz to (pseudo- 1 kHz...

  • Page 193: Example Of Connection With Dedicated Flash Programmer

    Figure 14-3. Example of Connection with Dedicated Flash Programmer Dedicated flash programmer Dedicated flash programmer Note Connect this pin when the system clock is supplied from the dedicated flash programmer. If a resonator is already connected to the X1 pin, the CLK pin does not need to be connected. Caution The V pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer.

  • Page 194: Pin Connection List

    If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the µ PD78F9801. For details, refer to the manual of Flashpro III/Flashpro IV. Signal Name VPP1 Output Write voltage −...

  • Page 195: On-board Pin Processing

    In normal operation mode, input 0 V to the V (TYP.) is supplied to the V pin, so perform either of the following. Connect a pull-down resistor (RV Use the jumper on the board to switch the V pin connection example is shown below. Figure 14-4. V µ...

  • Page 196: Signal Conflict (input Pin Of Serial Interface)

    Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 14-5.

  • Page 197: Signal Conflict (reset Pin)

    <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed.

  • Page 198: Connection Of Adapter For Flash Writing

    14.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 14-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O VDD2(LVDD) 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 µ...

  • Page 199: Wiring Example For Flash Writing Adapter With Pseudo-3-wire Method

    CHAPTER 14 Figure 14-9. Wiring Example for Flash Writing Adapter with Pseudo-3-Wire Method VDD2(LVDD) 44 43 42 41 40 39 38 37 36 35 34 µ PD78F9801 12 13 14 15 16 17 18 19 20 21 22 CLKOUT RESET VPP RESERVE/HS FRASH WRITER INTERFACE...

  • Page 200: Chapter 15 Instruction Set

    CHAPTER 15 This chapter lists the instruction set of the µ PD789800 Subseries. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instruction User’s Manual (U11047E). 15.1 Operation 15.1.1 Operand identifiers and description methods Operands are described in the “Operands”...

  • Page 201: Description Of "operation" Column

    15.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW: Program status word Carry flag...

  • Page 202: Operation List

    15.2 Operation List Mnemonic Operands r,#byte saddr,#byte sfr,#byte Note 1 Note 1 A,saddr saddr,A A,sfr sfr,A A,!addr16 !addr16,A PSW,#byte A,PSW PSW,A A,[DE] [DE],A A,[HL] [HL],A A,[HL+byte] [HL+byte],A Note 2 A,saddr A,sfr A,[DE] A,[HL] A,[HL+byte] Notes 1. Except r = A. 2.

  • Page 203

    Mnemonic Operands MOVW rp,#word AX,saddrp saddrp,AX Note AX,rp Note rp,AX Note XCHW AX,rp A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] ADDC A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (f register (PCC).

  • Page 204

    Mnemonic Operands SUBC A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] Remark One instruction clock cycle is one CPU clock cycle (f register (PCC). CHAPTER 15 INSTRUCTION SET Bytes...

  • Page 205

    Mnemonic Operands A,#byte saddr,#byte A,saddr A,!addr16 A,[HL] A,[HL+byte] ADDW AX,#word SUBW AX,#word CMPW AX,#word saddr saddr INCW DECW RORC ROLC SET1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit CLR1 saddr.bit sfr.bit A.bit PSW.bit [HL].bit SET1 CLR1 NOT1 Remark One instruction clock cycle is one CPU clock cycle (f register (PCC).

  • Page 206

    Mnemonic Operands CALL !addr16 CALLT [addr5] RETI PUSH MOVW SP, AX AX, SP !addr16 $addr16 $saddr16 $saddr16 $saddr16 $saddr16 saddr.bit,$addr16 sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 saddr.bit,$addr16 sfr.bit,$addr16 A.bit,$addr16 PSW.bit,$addr16 DBNZ B,$addr16 C,$addr16 saddr,$addr16 HALT STOP Remark One instruction clock cycle is one CPU clock cycle (f register (PCC).

  • Page 207: Instructions Listed By Addressing Type

    15.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte 1st Operand Note Note ADDC SUBC ADDC SUBC B, C saddr ADDC SUBC...

  • Page 208

    (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand ADDW SUBW CMPW MOVW saddrp Note Only when rp = BC, DE, or HL . (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 1st Operand A.bit sfr.bit...

  • Page 209

    (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic Instructions Compound Instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP CHAPTER 15 INSTRUCTION SET !addr16 [addr5] CALL CALLT User’s Manual U12978EJ3V0UD $addr16 DBNZ...

  • Page 210: Chapter 16 Electrical Specifications

    CHAPTER 16 = 25° ° ° ° C) Absolute Maximum Ratings (T Parameter Symbol Supply voltage Input voltage Output voltage Output current, high Output current, low Operating ambient temperature Storage temperature Notes 1. Make sure that the following conditions of the V flash memory is written.

  • Page 211

    CHAPTER 16 System Clock Oscillation Circuit Characteristics (T Resonator Recommended Circuit Crystal Oscillator frequency (f Oscillation stabilization time External X1 input frequency (f clock X1 input high-low-level OPEN width (t Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for the instruction execution time.

  • Page 212

    CHAPTER 16 = − − − − 40 to +85° ° ° ° C, V DC Characteristics (T Parameter Symbol Output current, high Output current, low Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current, high LIH1 LIH2 LIH3...

  • Page 213

    CHAPTER 16 = − − − − 40 to +85° ° ° ° C, V DC Characteristics (T Parameter Symbol Note 1 Supply current (Mask ROM Version) Note 1 Supply current ( µ PD78F9801) Notes 1. The power supply current does not include the current flowing through the on-chip pull-up resistors. 2.

  • Page 214

    CHAPTER 16 AC Characteristics = − − − − 40 to +85° ° ° ° C, V (1) Basic operations (T Parameter Symbol Cycle time (minimum instruction execution time) TI01 input frequency TI01 input high-/low-level width Interrupt input high-/low-level INTH INTL width RESET input low-level width...

  • Page 215

    CHAPTER 16 = − − − − 40 to +85° ° ° ° C, V (b) 3-wire serial I/O mode (T (i) SCK10 ...Internal clock output (when f Parameter Symbol SCK10 cycle time KCY1 SCK10 high-/low-level width SI10 setup time SIK1 SI10 hold time KSI1...

  • Page 216

    CHAPTER 16 AC Timing Measurement Points (Except X1 Input and USB Function) 0.8V 0.2V Clock timing X1 input TI Timing TI01 Interrupt Input Timing INTP0 RESET Input Timing RESET ELECTRICAL SPECIFICATIONS Measurement points INTL INTH User’s Manual U12978EJ3V0UD 0.8V 0.2V (MIN.) (MAX.)

  • Page 217

    CHAPTER 16 Serial Transfer Timing USB function: USBDM and USBDP rise/fall time USBDM, USBDP Transmission differential signal jitter USBDM, USBDP Differential output signal cross-over point, transmission EOP width, reception EOP width, and reception USB reset width USBDM, USBDP m = 1, 2 3-wire serial I/O mode: SCK10 SI10...

  • Page 218

    CHAPTER 16 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T Item Symbol Data hold supply voltage DDDR Release signal set time SREL Oscillation stabilization WAIT Note 1 time Notes 1. During the oscillation stabilization time, CPU operations are disabled to prevent them from becoming unstable upon the start of oscillation.

  • Page 219: Chapter 17 Package Drawings

    CHAPTER 17 44 PIN PLASTIC LQFP (10x10) NOTE Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition. PACKAGE DRAWINGS User’s Manual U12978EJ3V0UD detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 +0.08 0.37 −0.07...

  • Page 220: Chapter 18 Recommended Soldering Conditions

    For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 18-1. Surface Mounting Type Soldering Conditions µ...

  • Page 221: Appendix Adevelopment Tools

    APPENDIX A The following development tools are available for development of systems using the µ PD789800 Subseries. Figure A-1 shows the development tools. • Support of the PC98-NX series Unless otherwise stated, the µ PD789800 Subseries, which is supported by IBM PC/AT™ and compatibles, can be used for the PC98-NX series.

  • Page 222: A-1 Development Tools

    Language processing software · Assembler package · C compiler package · Device file · C library source file Flash memory writing environment Flash programmer Flash memory writing adapter Flash memory Notes 1. C library source file is not included in the software package. 2.

  • Page 223: Software Package

    A.1 Software Package SP78K0S Software tools for development of the 78K/0S Series are combined in this package. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files Part number: µ S××××SP78K0S ×××× in the part number differs depending on the OS used. Remark µ...

  • Page 224: Control Software

    ×××× in the part number differs depending on the host machine and operating system to be used. Remark µ S××××RA78K0S µ S××××CC78K0S ×××× AB13 PC-9800 series, IBM PC/AT compatibles BB13 AB17 BB17 3P17 HP9000 series 700 3K17 SPARCstation µ S××××DF789801 µ...

  • Page 225: Debugging Tools (hardware)

    A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of an application system using the In-circuit emulator 78K/0S Series. Supports a integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A The IE-78K0S-NS-A provides a coverage function in addition to the IE-78K0S-NS functions, thus In-circuit emulator...

  • Page 226: Debugging Tools (software)

    A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the Integrated debugger 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.

  • Page 227: Notes On Target System Design

    A.7 Notes on Target System Design Figures A-2 and A-3 show the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system.

  • Page 228: A-3 Connection Condition Of Target System (np-h44gb-tq)

    Figure A-3. Connection Condition of Target System (NP-H44GB-TQ) Emulation board IE-789801-NS-EM1 23 mm 10 mm Remarks 1. NP-H44GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. 2. TGB-044SAP is a product of TOKYO ELETECH CORPORATION. APPENDIX A DEVELOPMENT TOOLS Emulation probe NP-H44GB-TQ Conversion adapter...

  • Page 229: Appendix Bregister Index

    APPENDIX B REGISTER INDEX B.1 Register Index (Alphabetic Order of Register Name) 8-bit compare register 00 (CR00) ... 81 8-bit compare register 01 (CR01) ... 81 8-bit timer mode control register 00 (TMC00) ... 82 8-bit timer mode control register 01 (TMC01) ... 83 8-bit timer counter 00 (TM00) ...

  • Page 230

    APPENDIX B REGISTER INDEX Port mode register 2 (PM2) ... 69 Port mode register 4 (PM4) ... 69 Port output mode register 0 (POM0) ... 71 Port output mode register 1 (POM1) ... 71 Processor clock control register (PCC) ... 74 Pull-up resistor option register 0 (PU0) ...

  • Page 231: B.2 Register Index (alphabetic Order Of Register Symbol)

    B.2 Register Index (Alphabetic Order of Register Symbol) ADRCMP: Token address compare register ... 107 CR00: 8-bit compare register 00... 81 CR01: 8-bit compare register 01... 81 CSIM10: Serial operation mode register 10... 157 DIDCMP: Data/handshake PID compare register... 108 DRXCON: Data/handshake packet receive byte number counter ...

  • Page 232

    PU0: Pull-up resistor option register 0 ... 70 REMWUP: Remote wake-up control register ... 121 RXSTAT: Packet receive status register ... 111 SIO10: Transmit/receive shift register 10 ... 155 TCL2: Timer clock select register 2 ... 93 TIDCMP: Token PID compare register ... 106 TM00: 8-bit timer counter 00 ...

  • Page 233: Appendix C Revision History

    APPENDIX C The revision history is described below. The “Applied to” column indicates the chapters in each edition. Edition Major Revisions from Previous Edition Deletion of description “under development” for µ PD789800, since it has 2nd edition been developed Addition of GB-8ES type package Modification of recommended connection of unused pins in type of input/output circuit for each pin Addition of illustration in direct addressing...

  • Page 234

    Edition Major Revisions from Previous Edition Correction of address values in Figure 3-1 Memory Map ( µ µ µ µ PD789800) and Figure 3-2 Memory Map ( µ µ µ µ PD78F9801) Modification of Figure 5-3 External Circuit of System Clock Oscillator (b) External clock •...

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