Table of Contents
Advertisement
(4) Receive data bank
(a) Receive data PID (USBRD)
This is the receive data packet ID area. The data input to the data/handshake PID compare register
(DIDCMP) is stored here.
USBRD is read with an 8-bit memory manipulation instruction.
RESET input sets USBRD to 00H.
(b) Receive data address (USBR0 to USBR7)
This is an 8-byte register that stores the data/handshake packet transferred from the host.
USBR0 to USBR7 are read with an 8-bit memory manipulation instruction.
If the following combinations are used, they are read with a 16-bit memory manipulation instruction.
• USBR10: USBR0 and USBR1
• USBR32: USBR2 and USBR3
• USBR54: USBR4 and USBR5
• USBR76: USBR6 and USBR7
RESET input makes USBR0 to USBR7 undefined.
Symbol
07H
USBRD
USBR0
USBR1
USBR2
USBR3
USBR4
USBR5
USBR6
USBR7
The operation during reception appears as follows.
Packet from host controller
Response packet
1st byte
USBT00
8th byte
USBT07
The data packet from the host controller is stored in the USBT00 to USBT07 registers.
CHAPTER 8
Figure 8-5. Configuration of Receive Data Bank
USBPOB address
06H
05H
04H
ID area
Data area (8 bytes)
SETUP
DATA0
.
. .
. .
. .
. .
User's Manual U12978EJ3V0UD
USB FUNCTION
03H
02H
OUT
ACK
1st byte
USBT00
.
. .
. .
. .
. .
8th byte
USBT07
01H
00H
10H
11H
12H
13H
14H
15H
16H
17H
18H
DATA1
ACK
103
Advertisement
Table of Contents
