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Table 8-2 shows the state of each flag after receiving the USB reset signal and the Resume signal during the
bus idle state and bus suspend state.
Table 8-2. Flag of RXSTAT After Reception of USB Reset Signal and Resume Signal
Bus State
Idle
Suspend
(4) Data/handshake packet receive result store register (DRXRSL)
This register stores the data/handshake packet reception result.
Register contents are updated upon reception of data/handshake EOP.
DRXRSL is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets DRXRSL to 00H.
Figure 8-13. Format of Data/Handshake Packet Receive Result Store Register
Symbol
<7>
<6>
DRXRSL
CR16ER DBITER
CR16ER
0
CRC error did not occur in received data packet.
CRC error occurred in received data packet.
1
DBITER
0
Bit stuffing error did not occur in received data/handshake packet.
1
Bit stuffing error occurred in received data/handshake packet.
DBYER
0
Packet length of received data/handshake packet is normal.
1
Packet length of received data/handshake packet is abnormal.
DIDRST
Received data/handshake packet ID and value of data/handshake PID compare register (DIDCMP)
0
do not match.
1
Received data/handshake packet ID and value of DIDCMP match.
(5) Token packet receive result store register (TRXRSL)
This register stores the token packet reception status.
Register contents are updated upon reception of token packet EOP.
TRXRSL is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TRXRSL to 00H.
CHAPTER 8
Device State
Received Signal
Main system clock
USB reset
operation mode
Resume
STOP mode
USB reset
Resume
<5>
4
3
DBYER
0
0
CRC error detection (16-bit mode)
Received data/handshake packet length error detection
Data/handshake packet ID comparison result
User's Manual U12978EJ3V0UD
USB FUNCTION
RESMRX
0
1
0
1
2
<1>
0
0
DIDRST
0
Bit stuffing error detection
SE0RX
URESRX
1
1
1
0
1
1
1
0
Address
After reset
R/W
FF65H
00H
R/W
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