NEC uPD75P3116 Datasheet page 26

Mos integrated circuit 4-bit single-chip microcontroller
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Instruction
Mnemonic
Group
Subroutine
CALLA
Note
!addr1
stack control
CALL
Note
!addr
Note
CALLF
!faddr
Note
RET
Note
RETS
RETI
Note
Note The sections in double boxes are only supported in the Mk II mode. The other sections are only supported in the Mk I mode.
26
Operand
No. of Machine
Bytes
Cycle
(SP–6)(SP–3)(SP–4) ← PC
3
3
(SP–5) ← 0, 0, PC
(SP–2) ← X, X, MBE, RBE
PC
13-0
(SP–4)(SP–1)(SP–2) ← PC
3
3
(SP–3) ← MBE, RBE, PC
PC
13-0
(SP–6)(SP–3)(SP–4) ← PC
4
(SP–5) ← 0, 0, PC
(SP–2) ← X, X, MBE, RBE
PC
13-0
(SP–4)(SP–1)(SP–2) ← PC
2
2
(SP–3) ← MBE, RBE, PC
PC
13-0
(SP–6)(SP–3)(SP–4) ← PC
3
(SP–5) ← 0, 0, PC
(SP–2) ← X, X, MBE, RBE
PC
13-0
1
3
MBE, RBE, PC
PC
11-0
SP ← SP+4
X, X, MBE, RBE ← (SP+4)
PC
0, 0, PC
SP ← SP+6
1
3+S
MBE, RBE, PC
PC
11-0
SP ← SP+4
then skip unconditionally
X, X, MBE, RBE ← (SP+4)
PC
0, 0, PC
SP ← SP+6
then skip unconditionally
1
3
MBE, RBE, PC
PC
11-0
PSW ← (SP+4)(SP+5)
SP ← SP+6
0, 0, PC
PC
PSW ← (SP+4)(SP+5), SP ← SP+6
Data Sheet U11369EJ3V0DS
Operation
11-0
,
13
12
← addr1, SP ← SP–6
11-0
13, 12
← addr, SP ← SP–4
11-0
13, 12
← addr, SP ← SP–6
11-0
13, 12
← 000+faddr, SP ← SP–4
11-0
13, 12
← 000+faddr, SP ← SP–6
← (SP+1)
13, 12
← (SP)(SP+3)(SP+2)
← (SP)(SP+3)(SP+2)
11-0
← (SP+1)
13, 12
← (SP+1)
13, 12
← (SP)(SP+3)(SP+2)
← (SP)(SP+3)(SP+2)
11-0
← (SP+1)
13, 12
← (SP+1)
13, 12
← (SP)(SP+3)(SP+2)
← (SP+1)
13, 12
← (SP)(SP+3)(SP+2)
11-0
µ PD75P3116
Addressing
Skip
Area
Condition
*11
*6
*9
Unconditional

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