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Instruction
Mnemonic
Group
Bit transfer
MOV1
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
Arithmetic
ADDS
A, #n4
XA, #n8
A, @HL
XA, rp'
rp'1, XA
ADDC
A, @HL
XA, rp'
rp'1, XA
SUBS
A, @HL
XA, rp'
rp'1, XA
SUBC
A, @HL
XA, rp'
rp'1, XA
AND
A, #n4
A, @HL
XA, rp'
rp'1, XA
OR
A, #n4
A, @HL
XA, rp'
rp'1, XA
XOR
A, #n4
A, @HL
XA, rp'
rp'1, XA
Accumulator
RORC
A
manipulation
NOT
A
Increment/
INCS
reg
decrement
rp1
@HL
mem
DECS
reg
rp'
Operand
No. of Machine
Bytes
Cycle
CY ← (fmem.bit)
2
2
CY ← (pmem
2
2
CY ← (H+mem
2
2
(fmem.bit) ← CY
2
2
2
2
(pmem
2
2
(H+mem
A ← A+n4
1
1+S
XA ← XA+n8
2
2+S
A ← A+(HL)
1
1+S
XA ← XA+rp'
2
2+S
rp'1 ← rp'1+XA
2
2+S
A, CY ← A+(HL)+CY
1
1
XA, CY ← XA+rp'+CY
2
2
rp'1, CY ← rp'1+XA+CY
2
2
A ← A–(HL)
1
1+S
XA ← XA–rp'
2
2+S
rp'1 ← rp'1–XA
2
2+S
A, CY ← A–(HL)–CY
1
1
XA, CY ← XA–rp'–CY
2
2
rp'1, CY ← rp'1–XA–CY
2
2
A ← A
2
2
A ← A
1
1
XA ← XA
2
2
rp'1 ← rp'1
2
2
A ← A v n4
2
2
A ← A v (HL)
1
1
XA ← XA v rp'
2
2
rp'1 ← rp'1 v XA
2
2
A ← A v n4
2
2
A ← A v (HL)
1
1
XA ← XA v rp'
2
2
rp'1 ← rp'1 v XA
2
2
CY ← A
1
1
A ← A
2
2
reg ← reg+1
1
1+S
rp1 ← rp1+1
1
1+S
(HL) ← (HL)+1
2
2+S
(mem) ← (mem)+1
2
2+S
reg ← reg–1
1
1+S
rp' ← rp'–1
2
2+S
Data Sheet U11369EJ3V0DS
Operation
+L
.bit(L
))
7-2
3-2
1-0
.bit)
3-0
)) ← CY
+L
.bit(L
7-2
3-2
1-0
.bit) ← CY
3-0
n4
^
(HL)
^
rp'
^
XA
^
← CY, A
← A
, A
0
3
n-1
n
µ PD75P3116
Addressing
Skip
Area
Condition
*4
*5
*1
*4
*5
*1
carry
carry
*1
carry
carry
carry
*1
*1
borrow
borrow
borrow
*1
*1
*1
*1
reg = 0
rp1 = 00H
*1
(HL) = 0
*3
(mem) = 0
reg = FH
rp' = FFH
23
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