Sharp PC-1500 Technical Reference Manual page 19

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@ WAIT
CJ>U wait signal. A high on this line
stops
t he clock
' 1 >
so
that the CPU halts it>
operation.
1 \s
soon "'
WA IT
turns
lo", the Cl'U
rcM1mcs
the operation.
Rt1sic CIOCk
4>0$ / \ ' -_ __,/
\'--___, /
\'--__, /
\'--___, / \
Clock
~
I
\~--'I \._ _ _ _ _ _ _ .....JI
\
\' l AIT
'-----------------------------~-~
NOTE. WA is
th~
Jlipllopdedi<:aled to WAIT. by which the WAIT input is received a1 the talhng
edge
or
the ctock 4>0$ Because the CPU operating clock 4> stops when WA is hogh. 1 1
makes the CPU
0
stoppe<j. consequently.
@
HO- H7
I.CD
backphllc sig n;il o utp uc.
As
t he liq uid crys tal tfaplay
(lCf>l
is d ri,cn
by
ba ckplate signals and
scg1ncnt
signa1s. the
( 'l>U
contro ls the backplate sign;,d s.
@
VA, VB, VM, VDIS
I .CD backplate power
s11 pply inp1 11s.
@ HIN
Input signal
10
the counter from which tltc
LCD
backplalc signal;,
M0- 117
arc
generated. 1'om1all} . connected
10
pin
llA
or
the CPU.
@ HA
CPU
internal divider o u tput pin.
It
is used for the ba;ic clock t ha t drive, the
LCD
that
ctl nncctcd \Yic h tll!\
1
a nd the s.cgn1tnt signal gcncrating l.SJ.
@ D ISP
l .('f)
on/ off control l\ignal output \vhich
ca1l
be set or reset
by n1cans < lf instruct
ion.
@
BFO, BFI
BF nipOo p o utput ( llFO) and input ( BFI). The HI' OipOop is rc"Sct bi• t he OFF
instruction from the
CPU.
and "ill
be
set when the input 13FI is turned to high
level.
ll F O is in low level when the BF OipOop is set and in high level when
R'.SCI.
A s VGG is power supply to the BF OipOop. the conlent' or the OipOop are retained as
lo11g
as
VGG
is
in supply.
Norrnally.
it is
u~cd
for
rncn1ory backup
systcn1.
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