Sharp PC-1500 Technical Reference Manual page 16

10
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4>0$
Through th is line can
be supplied
the clock 10 an external system since 1he clock in the
same ph;,sc as the CPU internal basic clock is on this line. Conncccio n of the 2.6M H1
crystal oscillator lo
XLO
and
XLI
will supply ihc clock of l.JMHz.
©RIW
Me 1nory \Vrite sigrHtl. . / \ lo\v on this line causes the C l>U
tc>
send data on L he data bus.
Q) OD
Ompul disable signal. A high on this line causes the C P U IO prohihi1 data ou1put 10 the
external device. It is used in
\Vriting
data ro the mernory.
4>0S
AOO -
AD15
I
~AEOof~
M E1
I
OD~--' '-------~-__,/
'
. ~----
'
I
' < . _ __
00-07' ......
----~<
MEMORY
OATA D >---- <
CPlJ
DATA
)>-----
'
~----~.--'
k4cmo1y < cad c·;cle
MenlOI'; ·1•ote eye ~
©RESET
C PU reset input. High stale or this signal 1 ·cscts the CPU and the con1cn1s of 1hc
address FFFEH is sci IO the register PH ;ind the contents of the address FFFFM lo the
rcgisier PL. When ii !urns from high to low level. it siarts program execut ion from the
address or !he program counter.
CD
NMI
Non1-maskablc in1 crrup1 input. High stale of this signa l causes in1crmp1 10 the CPU . to
\vhich the CPl J unconditionaJJy responds and starts the interrupt processing routine of
which high order byte address is represented by 1hc address FFFC H and low order
byre address by FFFD H.
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