Sharp LC-37AD5E Service Manual page 78

LC-37AD5E
Pin No. Pin Name
17 CAS
16 WE
15 LDQM
39 UDQM
2 DQ0
4 DQ1
5 DQ2
7 DQ3
8 DQ4
10 DQ5
11 DQ6
13 DQ7
42 DQ8
44 DQ9
45 DQ10
47 DQ11
48 DQ12
50 DQ13
51 DQ14
53 DQ15
1, 14, 27 VDD
28, 41, 54 VSS
3, 9, 43, 49 VDDQ
6, 12, 46, 52 VSSQ
40 N.C/RFU
36 N.C
I/O
I Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
I Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
I Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
I
I/O Data inputs/outputs are multiplexed on the same pins.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
— Power for the input buffers and the core logic.
— Ground for the input buffers and the core logic.
— Isolated power supply for the output buffers to provide improved noise immunity.
— Isolated ground for the output buffers to provide improved noise immunity.
— This pin is recommended to be left No Connection on the device.
—
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Pin Function