Sharp LC-37AD5E Service Manual page 69

Pin No. Pin Name
62 DGI3
63 DGI2
64 DGI1
65 DGI0
66 DBI7
67 DBI6
68 DBI5
69 DBI4
70 DBI3
71 DBI2
72 DBI1
73 DBI0
74 GND3.3DRI
75 VSUP3.3DRI
76 GND3.3COM
77 VSUP3.3COM
78 XTALIN
79 XTALOUT
80 CLKOUT
81 VSO
82 HSO
83 SCL
84 SDA
85 GND3.3FL
86 VSUP3.3FL
87 P2-0
88 P2-1
89 P2_2
90 P2_3
91 P2_4
92 P2_5
93 OSDV
94 OSDH
95 GND3.3IO1
96 VSUP3.3IO1
97 OSDCLK
98 PSDFSW
99 OSD_HCS1/P3_6
100 P3_7
101 P3_5
102 P3_4
103 OSD_B1
104 OSD_B0
105 P3_3
106 P3_2
107 OSD_G1
108 OSD_G0
109 OSD_R3/P3_1
110 P3_0
111 OSD_R1
112 OSD_R0
113 GND3.3IO1
114 VSUP3.3IO1
115 PCS5/P2_7
116 PCS4/P2_6
117 PCS3/P4_1
118 PCS2/P4_0
119 PCS1/P4_3
120 PCS0/P4_2
121 PCLK2
122 PCLK1
123 GND1.8DIG
124 VSUP1.8DIG
125 LVDSA_4P
I/O
I Digital Video Green 3 Input.
I Digital Video Green 2 Input.
I Digital Video Green 1 Input.
I Digital Video Green 0 Input (LSB).
I Digital Video Blue 7 Input.
I Digital Video Blue 6 Input.
I Digital Video Blue 5 Input.
I Digital Video Blue 4 Input.
I Digital Video Blue 3 Input.
I Digital Video Blue 2 Input.
I Digital Video Blue 1 Input.
I Digital Video Blue 0 Input (LSB).
— Ground Digital Ram Interface.
— Supply Voltage Digital Ram Interface, 3.3 V.
— Ground Common.
— Supply Voltage Common, 3.3V.
I Analog Crystal Input.
O Analog Crystal Output.
O Digital 20MHz Clock Output. (Test point)
O Vertical Sync Output, Frontend. (Test point)
O Horizontal Sync Output, Frontend. (Test point)
I/O I2C Bus Clock Input/Output.
I/O I2C Bus Data Input/Output.
— Ground Flash.
— Supply Voltage Flash, 3.3 V.
I AVLINK_1 (AVLINK(BL_ERR))
I AVLINK_2 (AVLINK(POW_ERR))
I IRIN (Remote Control Input)
I KEY_PSW (Power SW Input)
O V_TXD (RS232C TX)
I V_RXD (RS232C RX)
I/O Graphic Vertical Sync Input/Output.(Test point)
I/O Graphic Horizontal Sync Input/Output.(Test point)
— Ground Digital Input/Output Port 1.
— Supply Voltage Input/Output Port 1, 3.3 V.
I/O Graphic Clock Input/Output.
I/O Graphic Fast Switch Output.
O Graphic Half Contrast 1 Output
I HOTP_CONT1 (HDMI Insertion/Removal Detection)
I HOTP_CONT0 (HDMI Insertion/Removal Detection)
O HDMI_INT_I (Interrupt from Receiver)
O Graphic Blue 1 Input/Output.
O Graphic Blue 0 Input/Output
O HDMI_INT_I (Interrupt from Receiver)
O Graphic Green 2 Input/Output
O Graphic Green 1 Output. (Test point)
O Graphic Green 0 Output. (Test point)
I BL_ERR Signal Input.
O DTM_IRQI (Interrupt from DTV)
O Graphic Red 1 Output. (Test point)
O Graphic Red 0 Output. (Test point)
— Ground Digital Input/Output Port 1.
— Supply Voltage Input/Output Port 1, 3.3 V.
I/O FPGA Serial data.
O FPGA Serial clock.
O Select 3 DE2 Output.
I Detect S-terminal.
O Select 1 H Output.
O Select 1 V Output.
O PCLK2 (Not used)
O VCT_PCLKO
— Ground Digital Core.
— Supply Voltage Digital Core, 1.8 V.
O LVDS Channel 1 bit 4 Positive Output.
5 – 10
Pin Function
LC-37AD5E