winsonic MFC1045S-XN40C User Manual page 14

6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Receiver Clock
LVDS Receiver Data
Vertical Active Display Term
Horizontal Active Display Term
Note (1) Since this assembly is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this assembly would operate abnormally.
DE
DCLK
DE
DATA
Panel Specification
Item
Frequency
Input cycle to
cycle jitter
Setup Time
Hold Time
Frame Rate
Total
Display
Blank
Total
Display
Blank
INPUT SIGNAL TIMING DIAGRAM
T
vd
T
h
T
c
T
hb
Symbol Min. Typ.
1/Tc 55 65
Trcl -
Tlvsu 600
Tlvhd 600
Fv 50 60
Tv 806
770
Tvd 768 768
Tvb 2 38
Th 1100 1344
Thd 1024 1024
Thb 76 320
T
v
T
hd
Valid display data (1024 clocks)
Max. Unit
75 MH
Z
- 200 ps
- - ps
- - ps
70 Hz
950 Th
768 Th
182 Th
1800 Tc
1024 Tc
776 Tc
T
vb
Note
Tv=Tvd+Tvb
-
-
Th=Thd+Thb
-
-