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5.2 BLOCK DIAGRAM OF INTERFACE
R0-R7
G0-G7
B0-B7
DE
Host
Graphics
Controller
R0~R7
: Pixel R Data ,
G0~G7
: Pixel G Data ,
B0~B7
: Pixel B Data
DE
: Data enable signal
Note (1) The system must have the transmitter to drive the assembly.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Panel Specification
TxIN
PLL
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
,
CN1
Rx0+
51
100pF
Rx0-
51
Rx1+
51
100pF
Rx1-
51
Rx2+
51
100pF
Rx2-
51
Rx3+
51
100pF
Rx3-
51
CLK+
51
100pF
CLK-
51
LVDS Receiver
THC63LVDF84A
RxOUT
R0-R7
G0-G7
B0-B7
DE
DCLK
PLL
Timing
Controller
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