Yamaha RX-V565 Service Manual page 76

RX-V565/HTR-6250/AX-V565
Pin No. Function Name
1 RXOUT1
2 RX0
3 RX1
4 RX2
5 RX3
6 DGND
7 DVDD
8 RX4
9 RX5
10 RX6
11 DVDD
12 DGND
13 LPF
14 AVDD
15 AGND
16 RMCK
17 RBCK
18 DGND
19 DVDD
20 RLRCK
21 RDATA
22 SBCK
23 SLRCK
24 SDIN
25 DGND
26 DVDD
27 XMCK
28 XOUT
29 XIN
30 DVDD
31 DGND
32 MOUT
33 AUDIO
34 CKST
35 INT
36 RERR
37 DO
38 DI
39 CE
40 CL
41 XMODE
42 DGND
43 DVDD
44 GPIOO
45 GPI01
46 GPI02
47 GPI03
48 RXOUT2
* Input voltage: 1= -0.3 to 3.6V, Is =-0.3 to 5.5V
* Output voltage: 0= -0.3 to 3.6V
* Pins 2, 4, 5, 8, 9, 10, 24, 38, 39, 40, and 41 have an internal pull-down resistor (Pd).
Their level is fixed when they are unselected.
* Pins 32 and 33 are input pins for chip address setting when pin 41 is held at the low level.
* Pin 34 serves as the input pin for designating as the master or slave when pin 41 is held at the low level.
* Pin 35 serves as the input pin for configuring the I/O of pins 44 to 47 when pin 41 is held at the low level.
* The DVDD and AVDD pins must be held at the same level and turned on and off at the same timing to preclude latch-up conditions.
76
I/O
O RX0-6 input S/PDIF through output pin 1
5V withstand voltage TIL input level compatible S/PDIF input pin
l (pd)
5
(connected to GND when RX1 is set)
Co-axial compatible S/PDIF input pin
I(pd)
(supported demodulation sampling frequency of up to 96 kHz)
5V withstand voltage TIL input level compatible S/PDIF input pin
l (pd)
5
(connected to GND when RX1 is set)
l (pd) 5V withstand voltage TIL input level compatible S/PDIF input pin
5
Digital GND
Digital power supply (3.3V)
l (pd) 5V tolerable TIL input level compatible S/PDIF input pin
5
l (pd) 5V tolerable TIL input level compatible S/PDIF input pin
5
l (pd) 5V tolerable TIL input level compatible SIPDIF input pin
5
Digital power supply (3.3V)
Digital GND
O PLL loop filter connection pin
Analog power supply (3.3V)
Analog GND
O R system clock output pin (VCO, 512fs, XIN)
O/I R system bit clock 1/0 pin (64fs)
Digital GND
Digital power supply (3.3V)
O/I R system LR clock 1/0 pin (fs)
O Serial audio data output pin
O S system bit clock output pin (16fs, 32fs, 64fs, 128fs)
O S system LR clock output pin (fs/4, fs/2, fs, 2fs)
l External serial audio data input pin
5
Digital GND
Digital power supply (3.3V)
O Oscillation amplifier clock output pin
O Output pin connected to the resonator
I External clock input pin. connected to the resonator (12.288 MHz or 24.576 MHz)
Digital power supply (3.3V)
Digital GND
I/O Emphasis information II input fs monitor output II chip address setting input pin
I/O Channel status bit 1 output II chip address setting input pin
I/O Clock switching transition period signal output II master/slave setting input pin
I/O Microcontroller interrupt signal output II pins 44-48 I/O setting input pin
O PLL lock error and data error flag output pin
O CCB microcontroller I/F, read data output pin (3-state)
l
CCB microcontroller I/F, write data input pin
5
l CCB microcontroller I/F, chip enable input pin
5
l CCB microcontroller I/F, clock input pin
5
l System reset input pin
5
Digital GND
Digital power supply (3.3V)
O/I General-purpose I/O pin II selector input pin (output referred to RMCK pin)
O/I General-purpose I/O pin II selector input pin (output referred to RBCK pin)
O/I General-purpose I/O pin II selector input pin (output referred to RLRCK pin)
O/I General-purpose I/O pin II selector input pin (output referred to RDATA pin)
O RX0-6 input S/PDIF through output pin 2
Detail of Function