Table of Contents
Advertisement
QQ
3 7 63 1515 0
IC401 M30622MGP-A57FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4))
Pin No.
1
2
3
4
5
6
7
SOURCE SEL1
8
9
10
11
12
13
14
15
16
17
18
SOURCE SEL2
19
20
TE
L 13942296513
21
22
23
24
25
EFFECTOR S0
26
EFFECTOR S1
27
EFFECTOR S2
28
EFFECTOR SEL
29
30
31
32
CD POWER
STBY LED/FAN
33
34
USB SERIAL CTS0
35
USB SERIAL TXD0
36
USB SERIAL RXD0
37
38
USB SERIAL RTS0
39
40
41
42
TBL SENSE
www
43
44
45
.
46
47
48
http://www.xiaoyu163.com
Pin Name
I/O
XRST
O
Reset signal output to the digital signal processor "L":reset
MMUTE
O
Control port for the digital signal processor motor driver mute
CD CCE
O
Chip enable contor port to the digital signal processor
SIRCS
I
Remote control signal input
CD CLK
O
Serial date transfer clock signal output to the digital signal processor
MP3 IREQ
I
Digital signal decoder request pin to master control
Select function input for effector mode (CD/USB/Video in: "L",
O
Tuner/Tape/Audio in: "H")
BYTE
—
Ground pin
CNVss
—
Ground pin
XC IN
I
Sub system clock input (32.768 kHz)
XC OUT
O
Sub system clock output (32.768 kHz)
System reset signal input from the reset signal IC "L": reset After the power
RESET
I
supply rises, "L" is input for several hundreds msec and then change to "H".
X OUT
O
Main system clock output (5 MHz)
VSS
—
Ground pin
X IN
I
Main system clock input (5 MHz)
VCC
—
Power supply pin (+3.3 V)
NMI
I
Non-maskable interrupt input
Select function input for effector mode (CD/USB/Tuner/Tape: "H",
O
Audio in/Video in: "L")
SBSY
I
Subcode sync detection signal input from the digital signal processor
AC CUT
I
AC off detection signal input from the reset signal IC "L": AC Cut detected
BUS3
I/O
Data bus line for CD communication with master control
BUS2
I/O
Data bus line for CD communication with master control
BUS1
I/O
Data bus line for CD communication with master control
BUS0
I/O
Data bus line for CD communication with master control
O
Effector circuitry delay time selection bit 0 signal output
O
Effector circuitry delay time selection bit 1 signal output
O
Effector circuitry delay time selection bit 3 signal output
O
Effector circuity bypass control signal output "H": bypass
IIC CLK
I/O
Clock signal for IIC communication between Master controller and Display controller
IIC DATA
I/O
Data signal for IIC communication between Master controller and Display controller
USBRST
O
Reset signal output to USB control IC "L": reset
O
Power on/off control signal output to BU section "H": power on
O
LED drive signal output of power indicator and fan on/off control port
CONTROL
I
Serial send control signal input from USB IC
O
UART serial transmission data line signal output to USB IC
I
UART serial reception data line signal output from USB IC
GC RESET
O
Reset signal output to display control IC "L": reset
O
Serial receive control output from USB IC
SEL SW
O
USB and CD control switch CD (H)/USB (L)
USB PWR
O
Power on/off control signal output to USB section Power On: H
OPEN SW
I
Eject detection signal input from the CD mechanism
I
Disc tray position detection signal input from the CD mechanism
E-3
I
Disc tray status detection signal input from the CD mechanism
x
ao
E-2
I
Disc tray status detection signal input from the CD mechanism
y
E-1
I
Disc tray status detection signal input from the CD mechanism
i
TMF
O
CD mechanism turning motor control signal output
TMR
O
CD mechanism turning motor control signal output
LMF
O
CD mechanism loading motor control signal output
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
HCD-GTX66/GTX77
2 9
9 4
2 8
Pin Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
69
Hide quick links:
Advertisement
Table of Contents
