Sony HCD-GTX66 Service Manual page 68

HCD-GTX66/GTX77
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Pin No. Pin Name
51 PIO3
52 VSS1
53 VDDT3
54 SBSY
55 SBOK/FOK
56 IPF
57 SFSY/LOCK
58 ZDET
59 GPIN
60 MS
61 DOUT (PO6)
62 AOUT1 (PO7)
63 BCK (PO8)
64 LRCK (PO9)
65 AIN (PI4)
66 BCKi (PI5)
67 LRCKi (PI6)
68 VDD1
69 VSS
70 AWRC
71 PVDD3
72 PDO
73 TMAXS
74 TMAX
TE
L 13942296513
75 LPFN
76 LPFo
77 PVREF
78 VCOF
79 PVSS3
80 SLCo
81 RFi
82 RFRPi
83 RFEQo
84 VRo
85 RESiN
86 VMDiR
87 TESTR
88 AGCi
89 RFo
90 RVDD3
91 LDo
92 MDi
93 RVSS3
94 FNi2 (C)
95 FNi1 (A)
96 FPi2 (D)
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97 FPi1 (B)
98 TPi (F)
99 TNPC
.
100 TNi (E)
68
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I/O
I Gate signal input from the USB controller
— Ground pin
— Power supply pin (+3.3 V)
O Subcode block sync signal output to the system controller
O Not used in this set. (Open)
O Not used in this set. (Open)
O Not used in this set. (Open)
O Zero detection signal output Not used in this set. (Open)
I Not used. (Connected to ground.)
I Microcomputer interface mode selection signal input Fixed at "H" in this set.
O Digital audio data output Not used in this set. (Open)
O Audio data output Not used in this set. (Open)
O Bit clock signal output to the USB controller
O L/R sampling clock signal output
I Digital audio data input from the USB controller
I Bit clock signal input from the USB controller
I L/R sampling clock signal input from the USB controller
— Power supply pin (+1.5 V)
— Ground pin
— Not used in this set. (Open)
— Power supply pin (+3.3 V)
O Phase error margin signal between EFM signal and PLCK signal output
O TMAX detection signal output Not used in this set. (Open)
O TMAX detection signal output
I Inverted signal input from the operation amplifier for PLL loop filter
O Signal output from the operation amplifier for PLL loop filter
I Reference voltage (+1.65 V) input
O VCO filter output
— Ground pin
O EFM slice level output
I RF signal input
I RF ripple signal input
O EFM slice level output
O Reference voltage (+1.65 V) output
O External resistor connection pin
O Reference voltage (+1.65 V) output for automatic power control circuit
O Low-pass filter terminal for RFEQO offset correction
I RF signal amplitude adjustment amplification input
O RF signal generation amplification output
— Power supply pin (+3.3 V)
Laser diode on/off control signal output to the automatic power control circuit
O
"H": laser diode on
I Light amount monitor input from the laser diode of optical pick-up block
— Ground pin
I Main beam (C) input from the optical pick-up block
I Main beam (A) input from the optical pick-up block
I Main beam (D) input from the optical pick-up block
I Main beam (B) input from the optical pick-up block
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I Sub beam (F) input from the optical pick-up block
O External capacitor connection pin
i
I Sub beam (E) input from the optical pick-up block
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2 9
8
Pin Description
Q Q
3 6 7 1 3 1 5
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9