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3 7 63 1515 0
Pin No.
91
PGIO0
92
PGIO8
93
PGIO2/VSYNC/CSYNC
94
AVDD PLL
95
NC
96
NC
97
NC
98
AGND PLL
99
VSS
100
NC
101
PGIO3/HSYNC
102
VDD3
103
PGIO1/VCK-OUT
104
VSS
105
GCK
106
VCK-IN
107
GCKOUT/DA-EMP
108
DA-LRCK
109
VDDMAX-OUT
110
DA-DATA
111
DA-BCK
112
HD-OUT
113
HRDY
TE
L 13942296513
114
HINT
115
CDG-SCK
116
VSS
117
HCK
118
VDD3
119
HD-IN
120
VDD3
121
HSEL
122
CDG-SDATA
123
CDG-VFSY
124
CDG-SOS1
125
NC
126
NC
127
NC
128
NC
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Pin Name
I/O
I/O
Not used
I/O
Not used
O
Vertical synchronized signal of video signal
–
+3.3V Power supply
–
Not used
–
Not used
–
Not used
–
Ground
–
Ground
–
Not used
O
H. sync signal output
–
+3.3V Power supply
I/O
Not used
–
Ground
I
Not used
I
Main clock for video signal processer
O
Not used
O
Digital Audio Left or Right channel selection clock
O
Fix the maxium output voltage certain output pins (Connected to +5V)
O
Digital Audio data
O
Digital Audio bit clock
O
Serial Data output from CL680 to the host MPU
O
Ready signal CL680 is ready for communication to the host MPU
O
Request signal for interrupting the host MPU
I/O
Not used
–
Ground
I
Host clock : referance signal for the host bus interface
–
+3.3V Power supply
I
Serial Data output ftom the host MPU to CL680
–
+3.3V Power supply
I
Select data or address of the host MPU
I
Ground
I
Ground
I
Ground
–
Not used
–
Not used
–
Not used
–
Not used
x
ao
y
i
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2 9
9 4
2 8
Function
1 5
0 5
8
2 9
9 4
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9 9
2 8
9 9
53
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