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HCD-VX99
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3 7 6 3 1 5 1 5 0
7-23. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD3008Q) (BD Board)
Pin No.
Pin Name
I/O
1
DVDD0
—
Digital power supply
2
XRST
I
System reset
3
MUTE
I
Muting selection pin
4
DATA
I
Serial data input, supplied from CPU
5
XLAT
I
Latch input, supplied from CPU
6
CLOK
I
Serial data transfer clock input, supplied from CPU
7
SENS
O
SENS output
8
SCLK
I
SENS serial data read-out clock
9
ATSK
I/O
Input pin for anti-shock (Ground)
10
WFCK
O
WFCK (Write Frame Clock) output (Not used)
11
XUGF
O
XUGF output (Not used)
12
XPCK
O
XPCK output (Not used)
13
GFS
O
GFS output (Not used)
14
C2P0
O
C2PO output
15
SCOR
O
Sub-code sync output
16
CM4
O
4.2336MHz output (Not used)
17
WDCK
O
48-bit slot D/A interface word clock (Not used)
18
DVSS
—
Digital ground
19
COUT
O
Numbers of track counted signal output (Not used)
20
MIRR
O
Mirror signal output (Not used)
21
DFCT
O
Defect signal output (Not used)
T E
L
1 3 9 4 2 2 9 6 5 1 3
22
FOK
O
Focus OK output (Not used)
23
PWM1
I
(Not used)
24
LOCK
I/O
GFS in sampled by 460Hz (Not used)
25
MDP
O
Output to control spindle motor servo
26
SSTP
I
Input signal to detect disc inner most trak
27
FST0
O
2/3 divider output (Not used)
28
DVDD1
—
Digital power supply
29
SFDR
O
Sled drive output
30
SRDR
O
31
TFDR
O
Tracking drive output
32
TRDR
O
33
FFDR
O
Focus drive output
34
FRDR
O
35
DVSS1
—
Digital ground
36
TEST
I
TEST pin connected normally ground
37
TES1
I
38
VC
I
Center voltage input
39
FE
I
FOCUS error signal input
40
SE
I
Sled error signal input
w w w
Function
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8
Pin No.
Pin Name
41
TE
42
CE
43
RFDC
44
ADI0
45
AVSS0
46
IGEN
47
AVDD
48
ASYO
49
ASYI
50
RFAC
51
AVSS1
52
CLTV
53
FILO
54
FILI
55
PCO
56
AVDD1
57
BIAS
58
VCTL
59
V16M
60
VPCO
61
DVDD2
Q
Q
62
ASYE
3
7
6
3
63
MD2
64
DOUT
65
LRCK
66
PCMD
67
BCLK
68
EMPH
69
XTSL
70
DVSS2
71
XTAI
72
XTAO
73
SOUT
74
SOCK
75
XOCT
76
SQSO
77
SQCK
78
SCSY
79
SBSO
80
EXCR
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.
48
48
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2
4
9
9
8
I/O
Function
I
Tracking error signal input
I
Center servo analog input
I
RF signal input
O
Test pin (Not used)
—
Analog ground
I
Power supply pin operational amplifiers
—
Analog power supply
O
EFM full swing output
I
Asymmetry comparate voltage input
I
EFM signal input
—
Analog ground
I
Control voltage input for master VCO
O
Filter output for master PLL
I
Filter input for master PLL
O
Charge-pump output for master PLL
—
Analog power supply
I
Asymmetry circuit constant current input
I
Control voltage input for variable pitch PLL
I/O
16.9344MHz output (Not used)
O
Charge-pump output for variable pitch PLL (Not used)
—
Digital power supply
I
Asymmetry circuit ON/OFF (Connected to +5V.)
1
5
1
5
0
8
9
2
4
I
Digital-out ON/OFF control (Connected to +5V.)
O
Digital-out output
O
48-bit slot D/A interface, LR clock output
O
48-bit slot D/A interface, Serial deta output
O
48-bit slot D/A interface, bit clock output
O
Playback disc output in emphasis mode (Not used)
I
X'tal selection input pin
—
Digital ground
I
X'tal oscillator circuit input
O
X'tal oscillator circuit output (Not used)
O
O
(Not used)
O
O
Sub-Q serial output
I
Clock input for SQSO read-out
I
Sub-code input
O
Sub-P through Sub-W serial output (Not used)
I
Clock input for SBSO read-out
m
c o
2
9
9
9
8
2
9
9
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