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QQ
3 7 63 1515 0
Pin No.
Pin Name
57
PDCLK
58
VSS
59
VSYNC
60
HSYNC
61
SO
62
FID
63
V
DD
64
XIICEN
TE
L 13942296513
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I/O
13.5MHz pixel data clock output pin.
This clock is obtained by 1/2 frequency-dividing SYSCLK.
O
Used only in the 16-bit pixel data mode
–
Digital ground
O
V.sync signal output
H.sync signal output
O
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the S0 serial-
O
out output pin.
When the XIICEN pin is "L", this pin is not used and sets into high impedance (Not used)
Field ID output.
When control register bit "FDS"="1", "L" indicates the first field and "H" indicates the
O
second field.
When control register bit "FDS"="0", "H" indicates the first field and "L" indicates the
second field
Digital power supply
–
Serial interface mode selection input pin. (Connected to digital power supply)
I
When "L", Pins 48 to 50, and 61 set into the I
When "H", Pins 48 to 50, and 61 set into the SONY SOP mode
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2 9
8
Function
2
C-BUS mode.
Q Q
3
6 7
1 3
1 5
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9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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